The assembly1 course taught every universal concept a CPU needs — registers, memory, the fetch-decode-execute cycle, the stack — using LC-3, an architecture built specifically so none of history's messiness would get in the way. This course exists to reintroduce that messiness, on purpose. Within a single year, 1975 and 1976, two real chips shipped that shaped an entire generation of home computers — and they solved the exact same problems LC-3 solved cleanly, under real financial and competitive pressure, in two almost opposite ways.

1975–76 — The Microprocessor Boom

In the early 1970s, Intel's 8080 was the microprocessor to build around — powerful for its time, and priced at $179, out of reach for most hobbyists and small companies. Two chips arrived within a year of each other specifically to disrupt that:

• MOS Technology 6502 (1975) — designed by Chuck Peddle and a small team who had left Motorola specifically to build something radically cheaper. It launched at $25 — a price cut so aggressive it was demonstrated by literally handing out chips at a trade show. That price point wasn't a side effect of the design; it was the design goal, and cpu8bit1-2 traces exactly how it shaped every architectural decision that followed.
• Zilog Z80 (1976) — designed by Federico Faggin, who had previously helped design the very Intel 8080 the Z80 was now competing against. Rather than starting from a clean slate, Faggin built the Z80 as a superset of the 8080 — every existing 8080 program would still run on it, while adding real new capability on top. cpu8bit1-5 covers exactly what that compatibility commitment cost, and what it bought.

Two chips, two completely different founding constraints — one built around a price target, one built around compatibility — and both shipped into the same booming, cash-strapped hobbyist and early home-computer market at almost the same moment.

A Quick Bridge — Baseline Vocabulary from assembly1

This course assumes the concepts assembly1 already built, rather than re-teaching them from zero. If any of the terms below feel unfamiliar, that course is the place to go back to first.

A First Preview: RISC vs. CISC

The 6502's minimalism — few registers, a small instruction set, most instructions executing in a small, predictable number of cycles — previews a design philosophy that would later be named RISC (Reduced Instruction Set Computing). The Z80's richness — many specialized instructions, more addressing modes, variable-length encodings that pack more capability into fewer lines of assembly — previews what would later be called CISC (Complex Instruction Set Computing).

This course names that connection here, deliberately early, and comes back to formalize it properly in cpu8bit1-11 — once both chips have actually been studied in enough depth for the comparison to mean something concrete, rather than just a label.

How This Course Is Structured

To keep the comparison genuinely even-handed, the 6502 and Z80 each get their own uninterrupted three-chapter block, covering identical ground in identical order:

• Chapters 2–4 — the 6502: design philosophy, registers & the stack, addressing modes
• Chapters 5–7 — the Z80: design philosophy, registers & the stack, addressing modes
• Chapter 8 — the same small routine, written and compared in both
• Chapter 9 — interrupts, revisiting the minimalism-vs-richness contrast one more time
• Chapter 10 — where these chips actually lived: real machines, real culture
• Chapter 11 — formalizing the RISC-vs-CISC throughline this chapter only previewed
• Chapter 12 — a capstone comparing a larger routine across both chips

Hands-On Exercises

cpu8bit1-1 named the 6502's $25 price target as "the founding fact of the whole chip." This chapter makes good on that claim — tracing exactly how a cost target turns into an actual, physical engineering constraint, and what MOS Technology chose to build (and not build) as a result.

The Team Behind the Chip

Chuck Peddle and several colleagues had been working at Motorola on the 6800, a capable but expensive processor. When Motorola declined to pursue a radically cheaper version of the idea, Peddle's team left and joined MOS Technology instead, determined to prove a genuinely low-cost, high-volume microprocessor was possible. The 6502, released in 1975, was that proof.

The Real Engineering Cost of Cheap — Die Size and Transistor Count

In 1975, a chip's manufacturing cost was driven heavily by two linked factors: die size (how much physical silicon each chip consumes) and yield (what fraction of chips cut from a wafer come out defect-free). A smaller die means more chips fit on a single wafer and a better yield, since a random manufacturing defect is less likely to land inside a smaller area. Both effects push the same direction: fewer transistors means a smaller, cheaper, higher-yield chip — not as an abstract design preference, but as literal manufacturing economics.

Once $25 was the target, transistor count stopped being a minor implementation detail and became the single number the whole design had to be justified against, line by line.

Roughly half the transistor budget, roughly half the general-purpose registers — this isn't a coincidence. Fewer registers means less on-chip storage circuitry, directly translating a smaller register file into real, measurable die-area savings.

"Do More With Less" — Concrete Design Choices

Every one of the following, covered in full over the next two chapters, traces back to the same transistor-budget pressure:

• A small register file (cpu8bit1-3) — one accumulator (A) plus two index registers (X, Y), instead of a larger general-purpose bank.
• Zero-page addressing (cpu8bit1-4) — a clever addressing trick that gets much of the speed benefit of extra registers without spending transistors on them.
• A fixed, hardware-managed stack confined to a single page of memory, rather than a more flexible (and more transistor-hungry) general mechanism.

What "Minimalism" Doesn't Mean

It's tempting to read "fewer transistors" as "less capable" or "a compromised chip" — that's not what happened here. The 6502 still includes everything a real program genuinely needs: arithmetic, memory access, branching, subroutine calls, a stack. Nothing essential was cut. What was cut was redundancy and luxury: extra general-purpose registers a program could often work around, more addressing modes than were strictly necessary, more elaborate (and more expensive) internal machinery than the actual workload demanded.

"Minimalism" here means every transistor included had to earn its place in a tight budget — not that the chip does less than it needs to.

Hands-On Exercises

cpu8bit1-2 named A, X, and Y as the 6502's general-purpose registers, and left the rest for here. This chapter completes the picture — the special-purpose registers that make the chip actually work (PC, SP, P), a real hardware stack that's genuinely better than assembly1-7's manual LC-3 approach in one way and more limited in another, and the concrete reason the small register file forces the addressing-mode cleverness cpu8bit1-4 covers next.

The Full 6502 Register Set

The Status Register — Richer Than N/Z/P

assembly1-4's N/Z/P condition codes were LC-3's own deliberately simplified teaching version of a real status register. The 6502's actual P register packs eight individual flag bits, several of which LC-3 simply never needed:

• N (Negative) and Z (Zero) — direct counterparts to two of LC-3's own three condition codes.
• C (Carry) — LC-3 never had one, because LC-3's registers were a full 16 bits wide, matching its own word size, so ordinary addition never needed to signal "this overflowed the register." The 6502's 8-bit registers make Carry essential — see below.
• V (Overflow) — a separate flag specifically for signed overflow, distinct from Carry's unsigned overflow signal — a distinction LC-3's simplified model never had to draw.
• D (Decimal mode) — switches addition/subtraction into binary-coded decimal, useful for real-world calculations (early point-of-sale and calculator-style applications) where exact decimal results matter more than raw binary speed.
• I (Interrupt disable) — a real hardware feature LC-3 never modeled at all.
• B — only meaningful in the copy of P pushed to the stack during an interrupt, distinguishing a software-triggered BRK from a real hardware interrupt.

Why the Carry Flag Matters So Much Here

The 6502 is an 8-bit CPU — its registers and internal data paths handle one byte (0–255) at a time — but its address bus is 16 bits, giving it a full 64KB address space. That split matters: any arithmetic on a number bigger than 255 has to be built by hand, one byte at a time, chaining the result of one 8-bit addition into the next using Carry:

CLC              ; clear Carry before starting a multi-byte add
LDA NUM1_LOW
ADC NUM2_LOW    ; add with carry — low bytes
STA RESULT_LOW
LDA NUM1_HIGH
ADC NUM2_HIGH   ; carry from the low-byte add feeds into this one
STA RESULT_HIGH

LC-3's own 16-bit-wide registers meant a value never needed to be split across two registers just to add it — this entire pattern, and the Carry flag it depends on, simply had no reason to exist in assembly1. It's a direct, concrete consequence of the 6502 being genuinely 8-bit in a way LC-3, built purely for teaching, never was.

The Stack — Real Hardware, Genuinely Constrained

assembly1-7 had to build PUSH and POP entirely out of ordinary ADD/STR/LDR instructions, because LC-3 provides no dedicated stack-pointer register at all. The 6502 is a real improvement here: SP is a genuine, dedicated hardware register, and the chip provides native push/pull instructions:

PHA   ; push the accumulator onto the stack
PLA   ; pull the top of the stack back into the accumulator
PHP   ; push the status register
PLP   ; pull the status register back

Compare that single PHA against assembly1-7's own multi-instruction manual push sequence — this is real, dedicated hardware doing in one instruction what LC-3 needed three for.

The constraint: SP is only 8 bits wide, not 16. It doesn't hold a full address — it holds just the low byte of one, and the high byte is permanently fixed to $01 by the hardware. This locks the entire stack to a single 256-byte region, page 1 (addresses $0100–$01FF), no matter what. The stack grows downward — SP decrements on every push, increments on every pull — the same downward-growing convention assembly1-7's own example already used.

Why So Few Registers Forced Clever Addressing

Three general-purpose registers — A, X, Y — is genuinely little working space. Adding more wasn't an option without breaking cpu8bit1-2's own transistor budget. Instead, the 6502's designers found a different way to get fast, flexible access to values without paying for more physical registers: a special, quick-access region of memory that instructions can reach with shorter encodings than ordinary memory access requires. cpu8bit1-4 covers this technique — zero-page addressing — in full, as the chip's real answer to "we can't afford more registers."

Hands-On Exercises

cpu8bit1-3 closed with a promise: with only three general-purpose registers, the 6502 needed another way to get fast, flexible access to values. This chapter delivers on it — zero page, the chip's real, concrete answer to a transistor budget that couldn't afford more registers, plus the rest of the addressing modes that make real 6502 programs practical.

Zero Page — The Chip's Real Answer

Addresses $0000–$00FF — the first 256 bytes of memory — get special treatment on the 6502. Because every address in that range fits in a single byte, an instruction accessing zero page only needs to encode one address byte instead of two. That shorter encoding means less to fetch and fewer internal cycles to compute the effective address — zero page is measurably faster than ordinary memory access, not just shorter to type.

The practical effect: with 256 available slots, zero page behaves like a bank of pseudo-registers, vastly larger than the 3 real ones (A, X, Y) the chip actually has — at a real cost (an extra memory access instead of a truly free register read), but a far smaller cost than physical registers would have added to the transistor budget cpu8bit1-2 already established as the chip's central constraint.

Absolute Addressing — Reaching the Full 64KB

Absolute addressing embeds a full, two-byte address directly in the instruction, reaching anywhere across the 6502's entire 64KB space. This is worth contrasting directly with assembly1-3's own PC-relative LD: LC-3 had to compute an address from an offset specifically because its instructions were a fixed 16 bits wide, with no room left over for a full standalone address. The 6502 doesn't have that problem — its instructions are variable length (1 to 3 bytes), so a full 2-byte address simply costs one extra byte in the instruction stream, not a fight for bits within a single fixed-width word.

LDA $0050    ; zero page — 2 bytes, address fits in one byte
LDA $1050    ; absolute — 3 bytes, a full two-byte address

Indexed Addressing — Zero Page,X and Absolute,X/Y

Adding X or Y to a base address turns either mode into an indexed one — the mechanism behind iterating over an array, with the index register playing a role similar to assembly1-3's own base+offset LDR, except the "offset" here is a whole register that changes every loop iteration rather than a fixed 6-bit constant baked into the instruction.

LDA $0050,X   ; zero page,X — base $0050 plus X
LDA $1050,X   ; absolute,X — base $1050 plus X, reaches the full 64KB

(Zero Page),Y — Indirect-Indexed: A Real Pointer Dereference

This is the 6502's most powerful addressing mode, and the direct answer to a problem assembly1-3's own indirect mode (LDI/STI) never fully solved: accessing an array whose starting address isn't known until the program actually runs.

A zero-page location holds a full 16-bit pointer — the low byte at the zero-page address itself, the high byte at the next one over. (zp),Y reads that pointer, then adds Y to the pointer's value to get the final effective address:

; zero page $10/$11 holds a pointer to $3000
LDA #$00
STA $10        ; low byte of the pointer
LDA #$30
STA $11        ; high byte of the pointer — together, $10/$11 hold $3000

LDY #$00
LDA ($10),Y   ; reads from $3000 + Y — a real runtime pointer dereference

This is genuinely more capable than LC-3's own LDI, which could follow a pointer but never combine that with an index in the same instruction. (zp),Y does both at once — exactly what's needed to walk through an array whose address is only known at runtime.

A related, less commonly needed mode, (zero page,X) — indexed-indirect — works the other way around: X is added to the zero-page address first (wrapping within zero page, the same way zp,X does), and whatever pointer sits at the resulting location is used directly, with no further offset. It shows up most often selecting between several fixed pointers — a jump table, for instance — rather than walking through an array.

Real Cycle-Cost Comparison

Zero page's own 3-cycle cost against absolute's 4 is the concrete, measurable version of "extra registers" this chapter opened with — a real, repeatable speed advantage for any value accessed often enough to be worth keeping in the first 256 bytes.

Hands-On Exercises

Chapters 2–4 covered the 6502 end to end. This chapter opens an identical three-chapter arc for the Z80 — design philosophy first, exactly as cpu8bit1-2 did — so the two chips stay genuinely comparable rather than lopsided. And the contrast starts immediately: where the 6502 was built by a team that left one company to chase a price target from a clean slate, the Z80 was built by a designer extending his own earlier work, under a completely different kind of constraint.

The Team Behind the Chip — Federico Faggin's Break From Intel

Federico Faggin had already helped design the Intel 4004, 8008, and — directly relevant here — the 8080 itself, before leaving Intel in 1974 to found Zilog alongside Ralph Ungermann. The Z80, released in 1976, wasn't Faggin encountering the 8080 as an outside competitor the way MOS Technology approached the market — it was its own original co-designer building a deliberate successor to it.

Built to Be a Superset — What "Compatible" Actually Meant

cpu8bit1-1's own Exercise 2 already touched this at a high level; here's the full picture. The Z80 was designed so that any existing 8080 machine code would run on it completely unchanged — while adding a substantial layer of new registers, instructions, and addressing modes on top. This produces a fundamentally different starting position than the 6502's own:

• The 6502 team could freely decide "we don't need this" — nothing existing constrained them, since they were designing from a genuine blank slate.
• The Z80 team could only add. Every instruction and register the 8080 already had needed to keep working exactly as before, whether or not it was still the cleanest way to do something — new capability had to be layered on top of that existing foundation, never used to replace or simplify it.

The CISC-Leaning Richness — Concrete Consequences

That compatibility mandate shows up as real, measurable richness once the 8080's own instruction set becomes the Z80's starting point rather than its ceiling:

• More instructions — the 8080 offered roughly 78 instruction types; the Z80, built as its superset, is commonly cited as offering around 158 — roughly double, all while remaining fully compatible with the original 78.
• More registers — a genuine shadow register set and dedicated index registers, both entirely new, covered in full in cpu8bit1-6.
• More addressing modes — covered in cpu8bit1-7.

Fitting roughly double the instructions into a design that still had to decode the 8080's original 256-opcode space required a real engineering trick: the Z80 reserves four special prefix bytes — CB, DD, ED, and FD — each one signaling "the next byte selects from an entirely separate table of additional instructions." It's a genuinely clever escape hatch, extending the instruction space far beyond what a single unprefixed byte could ever address — engineering cleverness aimed squarely at capability, the mirror image of the 6502's own cleverness aimed at cost.

Contrasted Directly With the 6502's Minimalism

Notice the transistor count moves in exactly the direction each chip's own founding constraint predicts: the 6502's cost target pushed it down, the Z80's added capability pushed it up — roughly double the 6502's own budget. Both chips are still answering the same underlying question cpu8bit1-2 raised — what does the transistor budget actually buy you — just pointed in opposite directions by two genuinely different starting pressures.

Hands-On Exercises

cpu8bit1-5 described the Z80's richness in the abstract — more instructions, more registers, more addressing modes. This chapter makes the register half of that claim concrete, following the exact structure cpu8bit1-3 used for the 6502, so the comparison stays direct and even-handed.

The Main Register Set — A, F, and the BC/DE/HL Pairs

Like the 6502, the Z80 has an accumulator (A) and a flags register (F) — but from there the two chips diverge sharply. Instead of two more single-purpose 8-bit registers (the 6502's X and Y), the Z80 provides six general-purpose 8-bit registers — B, C, D, E, H, L — and, crucially, they can be used either individually or combined into three genuine 16-bit register pairs: BC, DE, and HL.

This pairing is something the 6502 simply has no equivalent for at all — X and Y stay strictly 8-bit, always. The Z80's pairs make native 16-bit arithmetic possible directly:

LD  HL, $3000
LD  BC, $0005
ADD HL, BC     ; a single instruction adds two full 16-bit values

Compare that against cpu8bit1-3's own multi-byte addition example, which needed two separate 8-bit ADC instructions chained together through Carry because the 6502 has no native 16-bit arithmetic at all.

HL as a Pointer — Simpler Than Anything the 6502 Offers

HL in particular is routinely used as a direct memory pointer:

LD  HL, $3000
LD  A, (HL)     ; reads the byte AT the address held in HL — one register, one instruction

This is genuinely simpler than cpu8bit1-4's own (zp),Y — which required a pointer stored specifically in zero page, plus a separate index register, plus a two-step lookup. On the Z80, the pointer just lives directly in a 16-bit register; no zero-page indirection is needed at all.

The Shadow Register Set — A Genuinely Unique Feature

Here's where the Z80 does something neither the 6502 nor LC-3 offers any equivalent for: a complete second copy of A, F, and the BC/DE/HL pairs — the shadow (or alternate) register set, written A′, F′, B′C′D′E′H′L′. Only one set is active at any moment, and two special instructions swap between them:

• EXX — swaps the general-purpose BC/DE/HL with their shadow counterparts, all at once, in a single instruction.
• EX AF,AF′ — swaps A and F with their own shadow versions, separately from EXX.

The historical, documented purpose: fast interrupt handling. An interrupt routine could execute EXX to instantly gain an entirely fresh set of working registers, do whatever it needed to do, then EXX back — without ever needing to push the main registers onto the stack to protect them, and without ever needing to pop them back afterward. In practice, plenty of real Z80 programs (including software on the ZX Spectrum) simply used the shadow set as extra general-purpose storage rather than reserving it strictly for interrupts, since nothing in the hardware enforces how it's used — but the interrupt-speed use case is what motivated building it in the first place.

Index Registers — IX and IY

Two additional 16-bit registers, IX and IY, exist specifically to support indexed addressing — full treatment in cpu8bit1-7. A quick preview: LD A,(IX+5) reads the byte at whatever address IX holds, plus 5. These are exactly the registers behind two of cpu8bit1-5's own prefix bytes — IX-indexed instructions are signaled by the DD prefix, IY-indexed ones by FD. What was an abstract encoding mechanism in that chapter now has a concrete, working purpose.

Contrasted Against the 6502's Minimal Register File

Hands-On Exercises

This closes out the Z80 block. cpu8bit1-6 previewed IX/IY and HL-as-pointer; this chapter delivers the full addressing-mode picture, including the real cost the Z80's flexibility carries — and finishes with the stack, where the Z80 turns out to be a genuine synthesis of what LC-3 and the 6502 each did separately.

Register-Indirect Addressing — (HL), (BC), (DE)

cpu8bit1-6 already introduced (HL) as a direct pointer dereference. (BC) and (DE) work identically in principle — reading or writing whatever address the register pair currently holds — though in practice they're supported by a narrower set of instructions (mainly simple loads and stores), while HL remains the chip's general-purpose pointer workhorse, usable with far more of the instruction set. All three are simpler than assembly1-3's own LC-3 indirect mode (LDI), which required a two-step "read a pointer from a PC-relative address, then follow it" — here, the pointer already sits directly in a register, one step only.

Indexed Addressing With Displacement — IX+d and IY+d

IX and IY support a genuinely powerful addressing mode: a base register plus a signed 8-bit displacement (d, roughly -128 to +127), computed at execution time:

LD IX, $4000
LD A, (IX+5)   ; reads the byte at $4000 + 5 = $4005

This is a natural fit for accessing individual fields of a data structure at fixed offsets from a base pointer — IX holding the structure's address, d selecting which field — and unlike the 6502's own indexed modes from cpu8bit1-4, it isn't tied to zero page at all. IX and IY can point anywhere in the full 64KB space.

That flexibility has a real, measurable cost. Recall cpu8bit1-4's own cycle table for the 6502's addressing modes:

LD A,(IX+d) costs nearly four times what (HL) costs, and almost four times what the 6502's own (zp),Y costs for a broadly comparable "pointer plus offset" access. The Z80's version can reach anywhere in memory rather than needing a zero-page base — but that extra reach is paid for in real, per-instruction cycles, not just extra transistors.

The Stack — Real Hardware, Genuinely Flexible

cpu8bit1-3 covered the 6502's real but page-1-locked hardware stack, itself a genuine improvement over assembly1-7's entirely software-built LC-3 stack. The Z80's stack is a third point on that same spectrum: SP is a full 16-bit register, free to point anywhere in the 64KB address space — no fixed page, no artificial ceiling.

Push and pop are native instructions, and — reflecting cpu8bit1-6's own register pairing — they operate on a full 16-bit register pair at once, not a single byte the way the 6502's PHA does:

PUSH BC   ; pushes both B and C together, 16 bits in one instruction
POP  BC   ; pulls both back

The stack still grows downward — SP decrements on every push — the same convention assembly1-7's own LC-3 example and cpu8bit1-3's 6502 stack both already used.

Put side by side, the Z80's stack genuinely combines the best of both predecessors covered so far: LC-3's freedom to live anywhere, with real dedicated hardware doing the actual work — the flexibility of a software stack with the speed of a hardware one.

Hands-On Exercises

Chapters 2–7 studied each chip in isolation. This chapter puts them side by side for the first time — one identical task, written twice, so every difference on the page is a real difference in the chips themselves, not an accident of two separate examples. The task: sum five bytes stored in an array into a single running total.

The 6502 Version

ARRAY and SUM are both placed in zero page (cpu8bit1-4), so ARRAY,X below is genuinely zero-page,X indexed addressing, not the more expensive absolute,X form:

        LDX #0        ; X = array index = 0
        LDA #0        ; A = 0
        STA SUM      ; SUM = 0
LOOP    LDA SUM
        CLC          ; NEW — clear Carry before ADC (see warn-box below)
        ADC ARRAY,X  ; SUM += ARRAY[X] — zero-page,X (cpu8bit1-4)
        STA SUM
        INX          ; NEW — increment X (X++)
        CPX #5       ; NEW — compare X against 5, setting flags
        BNE LOOP      ; NEW — branch if the comparison found "not equal"
DONE    JMP DONE      ; the 6502 has no HALT — loop on itself forever

ARRAY   .BYTE 10,20,30,40,50   ; zero page, e.g. $10
SUM     .BYTE 0                    ; zero page, e.g. $20

Three genuinely new instructions here: INX (increment X), CPX (compare X against a value, setting the same flags cpu8bit1-3 already introduced), and BNE (branch if the Z flag is clear — "not equal"). Notice the loop needs three separate instructions — INX, CPX #5, BNE LOOP — just to advance and test the loop counter.

The Z80 Version

        LD HL, ARRAY  ; HL = pointer to the array's start (cpu8bit1-6)
        LD B, 5       ; B = remaining count = 5
        LD A, 0       ; A = 0
LOOP    ADD A, (HL)  ; A += the byte HL points to — register-indirect (cpu8bit1-7)
        INC HL       ; advance the pointer to the next byte
        DJNZ LOOP     ; NEW — decrement B, loop if B != 0, all in ONE instruction
        LD (SUM), A  ; store the final sum
DONE    JR DONE       ; the Z80 has no HALT either — loop on itself

ARRAY   DEFB 10,20,30,40,50
SUM     DEFB 0

One genuinely new instruction: DJNZ ("Decrement and Jump if Not Zero") — decrements B and branches back to the target in a single instruction if the result isn't zero, falling straight through if it is. It's a famous, well-known Z80 instruction, and this routine is exactly the pattern it exists for.

The Comparison

This is the concrete payoff cpu8bit1-5 and cpu8bit1-6 only described in the abstract. The 6502 needs three separate instructions (INX, CPX #5, BNE) to manage its loop counter every single iteration; the Z80's DJNZ folds decrement-compare-and-branch into one. That's the "richness" from cpu8bit1-5, made visible in real code rather than described as a slogan.

Fewer instructions on the Z80 side — but more total cycles per iteration, not fewer. Richness bought real code-density here, not raw speed.

Hands-On Exercises

assembly1-8 named interrupts only in passing — hardware signaling the CPU instead of the CPU repeatedly polling — and deliberately left the mechanism for later, more advanced material. This chapter is that material, on two real chips, and it's also where cpu8bit1-6's own shadow register preview finally gets to pay off for real.

The 6502's Interrupt Model — NMI, IRQ, BRK

The 6502 keeps interrupts as simple as everything else about it:

• IRQ (Interrupt Request) — triggered by external hardware wanting attention. Maskable: the I flag in the status register (cpu8bit1-3's own P register) can disable it entirely.
• NMI (Non-Maskable Interrupt) — reserved for events too critical to ever ignore. Cannot be disabled by any flag, and has its own dedicated vector.
• BRK — not a hardware event at all, but a real opcode a program can execute deliberately, triggering interrupt-like behavior in software. Historically used for debugging breakpoints and software-triggered system calls.

Whichever one fires, the sequence is identical: the CPU automatically pushes PC and the status register onto the stack — cpu8bit1-3's own page-1 stack, doing real work here — then jumps to a fixed handler address read from a small vector table near the very top of memory ($FFFA–$FFFF holds the NMI/RESET/IRQ vectors). The handler ends with RTI (Return from Interrupt), which pulls the status register and PC back off the stack, resuming exactly where the program left off. This is exactly why cpu8bit1-3's own status register includes the B flag — its entire purpose is letting the handler tell a genuine hardware IRQ apart from a deliberate software BRK once execution lands at that shared vector.

Only three vectors exist in total (NMI, RESET, and a shared IRQ/BRK vector) — one fixed handler address per category, no further sorting done by the hardware itself.

The Z80's Interrupt Model — NMI and Three Interrupt Modes

The Z80 also has an NMI, working much like the 6502's own (a fixed vector, unmaskable, automatic PC push). Its maskable interrupt is where the real richness shows up: the programmer selects one of three interrupt modes via a dedicated instruction (IM 0, IM 1, IM 2):

• IM 0 — the interrupting device itself supplies an instruction for the CPU to execute directly, usually a short call. This is inherited straight from 8080 compatibility (cpu8bit1-5's own founding constraint) — flexible, but the most primitive and least commonly used of the three.
• IM 1 — always jumps to one single fixed address ($0038), no matter which device interrupted. As simple as the 6502's own shared IRQ vector.
• IM 2 — the genuinely powerful mode. The CPU builds a 16-bit pointer by combining the high byte from a dedicated register (I, the interrupt vector register) with a low byte the interrupting device itself supplies, then looks up a full 16-bit handler address at that computed location in a table the programmer sets up in advance. Because the device-supplied byte is even, up to 128 distinct table entries are addressable — meaning every peripheral can get its own dedicated handler, instead of one shared entry point that then has to work out which device actually interrupted.

Where the Shadow Register Set Finally Pays Off

cpu8bit1-6 previewed EXX/EX AF,AF′ and named their real, historical purpose: fast interrupt entry. Now it's possible to see exactly why. A Z80 interrupt handler can execute a single EXX the moment it starts, instantly gaining a completely fresh, empty set of BC/DE/HL to work with — no need to push the main program's register values onto the stack to protect them first. A single EXX back at the end restores everything, and the handler returns.

A 6502 interrupt handler has no such option — anything it needs a register for, it must PHA/PLA (and similarly for X and Y, transferred through A first, since only A has native push/pull) around its own use of that register, each one a real, separate instruction costing real cycles on both entry and exit. The shadow set turns an entire category of that overhead into a single instruction.

Minimalism vs. Richness, a Third Time

This is the same contrast cpu8bit1-2 and cpu8bit1-5 established for the chips overall, and cpu8bit1-8 made concrete for loops — now showing up a third time, in a third domain entirely.

Hands-On Exercises

Chapters 2–9 studied both chips as pure engineering — transistors, registers, cycles, interrupts. This chapter grounds all of it in real machines and real markets: where minimalism and richness actually ended up, in products people bought by the millions. It's also where this course's own title finally gets fully explained — the "6510" has been sitting there unexplained since cpu8bit1-1.

The 6502's Real-World Footprint

• Apple II (1977) — Steve Wozniak's design, one of the machines that helped launch the personal computer industry as a mass-market category.
• Commodore PET, VIC-20, and Commodore 64 (the C64 in 1982) — one of the best-selling home computers of all time. The C64 specifically used the 6510, not a stock 6502 — a close variant adding an 8-bit I/O port used for bank-switching between ROM and RAM, but otherwise instruction-set identical to the 6502 this entire course has been teaching. This is finally the full explanation behind the course's own "6502/6510" title.
• Atari 2600 (1977) and later Atari 8-bit computers — the 2600 specifically used the 6507, a cut-down 6502 in a smaller, cheaper package with fewer address lines.
• Nintendo Entertainment System (1983 Japan / 1985 US) — powered by the Ricoh 2A03, a 6502 derivative widely reported to have had its decimal mode (cpu8bit1-3's own D flag) deliberately removed to avoid a licensing fee tied to that specific circuitry.

The Z80's Real-World Footprint

• Sinclair ZX Spectrum (1982) — hugely influential across the UK and European home computing scene, home to an enormous game library and demoscene.
• The MSX standard — a Japanese-led standardized home computer platform adopted by multiple manufacturers, all sharing Z80-based compatibility.
• Amstrad CPC series — another major European Z80-based home computer line.
• The original Nintendo Game Boy (1989) — powered by the Sharp LR35902, a genuine Z80 derivative that removes the shadow register set and IX/IY entirely, while adding a small number of its own new instructions.
• CP/M — the dominant business and professional operating system of the late 1970s and early 1980s, running primarily on Z80-based (and 8080-compatible) machines — a huge share of the Z80's real commercial footprint that had nothing to do with games at all, made possible directly by cpu8bit1-5's own 8080-compatibility story.

A Shared Pattern — Both Chips Spawned Cost/Licensing-Driven Derivatives

It's worth naming the parallel directly: both chips ended up inside an iconic games console via a derivative that deliberately removed something for cost or licensing reasons. The 6502 became the NES's 2A03 by losing decimal mode; the Z80 became the Game Boy's LR35902 by losing its entire shadow register set — the exact feature cpu8bit1-9 just finished showing off as the Z80's own genuine interrupt-handling advantage. Even in real hardware built directly from these two chips, the same kind of trade-off this whole course has been tracing — what's worth keeping, what's worth cutting — kept happening all over again, one generation later.

Both Are Still Actively Used Today

Neither chip is a purely historical curiosity. WDC (Western Design Center), founded by Bill Mensch — one of the 6502's own original co-designers named back in cpu8bit1-2 — still designs, produces, and licenses modern 6502-family cores today. The Z80 itself remained in continuous commercial production for an extraordinarily long stretch — decades — before shifting primarily toward licensed IP cores rather than standalone chips. Both architectures also have genuinely active hobbyist communities today, building homebrew computers, new games, and demos on real (or faithfully compatible) hardware, not just studying them as history.

Hands-On Exercises

cpu8bit1-1 named RISC and CISC in a single paragraph and immediately warned that neither term existed in 1975 or 1976. Nine chapters of real, concrete evidence later, it's time to formally define both terms properly and see exactly how much of that evidence actually supports the connection — including where it doesn't.

What RISC and CISC Actually Mean

RISC (Reduced Instruction Set Computing) favors a small number of simple, uniform instructions, each executing in a small, predictable number of cycles, with complex behavior built by combining several simple instructions in software rather than relying on one instruction that does more. It typically pairs this with a strict load/store discipline — exactly the principle assembly1-4 already taught as LC-3's own core design rule: ALU instructions only ever operate on registers, and memory is touched only through dedicated load/store instructions. The philosophy has a real, documented origin: the Berkeley RISC project (David Patterson, around 1980) and Stanford's MIPS project, both built specifically as a reaction against increasingly complex designs, using real measurements of real programs to argue that simpler, more uniform instructions could pipeline better and actually run faster in practice.

CISC (Complex Instruction Set Computing) favors a larger, richer instruction set, where individual instructions can perform more work — sometimes combining memory access and computation in a single instruction — with variable-length encoding and more specialized addressing modes. The term itself emerged largely as a retrospective label, applied to already-existing designs (the DEC VAX, and eventually x86) once RISC's contrasting philosophy gave critics a name to compare them against.

The 6502 as a Genuine RISC Precedent

Every piece of this course's own 6502 coverage lines up with RISC's later hallmarks:

• Small, uniform instruction count — 56 mnemonics (cpu8bit1-2), a genuinely small set.
• Narrow, predictable cycle costs — cpu8bit1-4's own table shows most 6502 instructions executing in a tight 2–7 cycle range, with nothing like the wide variance CISC-style complex instructions can have.
• A real load/store discipline — arithmetic routes through the accumulator, while LDA/STA are the dedicated instructions that actually touch memory. It's genuinely the same separation assembly1-4 taught, arrived at independently.

The strongest evidence, though, isn't just resemblance — it's a real, acknowledged historical line. Acorn Computers, the British company behind the BBC Micro (a 6502-based machine), went on to design ARM — one of the most successful real RISC architectures in computing history, today running in the overwhelming majority of the world's smartphones. ARM's own original designers, including Sophie Wilson and Steve Furber, have spoken publicly about the 6502's efficient, minimal design as a direct influence on ARM's earliest philosophy. This isn't an abstract parallel drawn by hindsight — it's a chip this course has been teaching for ten chapters, sitting in the actual, documented ancestry of a real, dominant modern RISC family.

The Z80 as a Genuine CISC Precedent

The Z80's own coverage lines up just as clearly on the other side:

• A large, rich instruction set — roughly 158 mnemonics (cpu8bit1-5) against the 6502's 56.
• Variable-length, prefix-extended encoding — the CB/DD/ED/FD mechanism (cpu8bit1-5) exists specifically to pack in more complexity than a single opcode byte could hold.
• Genuinely wide cycle-cost variance — cpu8bit1-7's own comparison showed (HL) at 7 cycles against (IX+d) at 19 — a spread the 6502 never approaches.
• Instructions that combine multiple logical steps — DJNZ (cpu8bit1-8) folds decrement, compare, and branch into one instruction, precisely the "do more per instruction" complexity RISC design deliberately avoids.

Here it's important to be precise rather than overreach: the Z80 is not a direct ancestor of x86 the way the 6502 is a direct, acknowledged ancestor of ARM. The Z80 descends from the 8080 via Zilog; Intel's own 8086 — the direct start of the x86 line — descends from the 8080 via Intel itself, as a rival, sibling design, not a child of the Z80. What genuinely connects them is philosophical, not genealogical: both emerged from the same instruction-rich, compatibility-driven tradition rooted in the 8080, and the same complexity-favoring impulse that produced the Z80's own richness is the same impulse that drove x86's own decades of accumulated complexity.

Why Neither Chip Is "Really" RISC or CISC

cpu8bit1-1 and cpu8bit1-5 both already flagged the basic anachronism — neither design team was building toward a checklist that didn't exist yet. But there's a sharper, more specific honesty worth adding here: the 6502's register count table above isn't just an anachronism, it's a genuine divergence. Real RISC design, once formalized, generally concluded that CPUs should have many registers — specifically to reduce how often a program needs to touch memory at all. The 6502 has the opposite: only 3, for a completely different reason (cpu8bit1-2's own transistor-cost pressure, not a deliberate strategy to minimize memory traffic). cpu8bit1-4's own zero-page trick is, in a sense, the 6502's real compensation for lacking the very thing later RISC design would have called for directly. The 6502 arrived at several genuinely RISC-shaped answers, from a starting motivation that had nothing to do with RISC's own actual reasoning — and diverges sharply on the one trait (register count) where the two philosophies' motivations point in opposite directions entirely.

Bridging to x86-64

assembly1-1 named x86-64 as the future course carrying "four decades of backward-compatible accretion" — and that lineage traces conceptually back to exactly the same instruction-rich, compatibility-first tradition this chapter just placed the Z80 within. Where this chapter's own Z80 material shows that tension at 1976 scale — roughly 158 instructions, a handful of prefix bytes — the still-unwritten x86-64 course picks up the same underlying story after another four decades of the same forces compounding, at a scale this course has only just begun to preview.

Hands-On Exercises

One task, one final time, on both chips: find the largest value in a 5-byte array. Unlike cpu8bit1-8's own summing routine, this one uses a real subroutine call — the first time either chip's real hardware stack (cpu8bit1-3, cpu8bit1-7) actually gets exercised by a working program in this course, rather than just described.

The 6502 Version

        LDX #1          ; start comparing from index 1
        LDA ARRAY      ; A = ARRAY[0]
        STA MAX        ; MAX = ARRAY[0] (the starting candidate)
LOOP    CPX #5
        BEQ DONE       ; NEW — branch if equal (complements BNE from cpu8bit1-8)
        LDA ARRAY,X    ; A = the next candidate — zero-page,X (cpu8bit1-4)
        JSR UPDATE_MAX ; NEW — call the subroutine (real stack use, cpu8bit1-3)
        INX
        JMP LOOP
DONE    JMP DONE       ; no HALT on the 6502 (cpu8bit1-8)

; --- Subroutine: UPDATE_MAX ---
; Input: A = candidate. Updates MAX in place if the candidate is bigger.
UPDATE_MAX
        CMP MAX        ; NEW — compare A against MAX (like SBC, but nothing stored)
        BCC SKIP       ; NEW — branch if Carry Clear (A < MAX)
        STA MAX        ; A >= MAX — update it
SKIP    RTS            ; NEW — return, pulling the address JSR pushed

ARRAY   .BYTE 10,50,30,80,20
MAX     .BYTE 0

New here: BEQ (branch if equal — the counterpart to cpu8bit1-8's own BNE), CMP (compares A against a value the same way ADC/SBC would, without storing a result), BCC (branch if Carry is clear), and — for the first time in this course — JSR/RTS, a real subroutine call and return, automatically using the page-1 stack cpu8bit1-3 only described until now.

The Z80 Version

        LD HL, ARRAY
        LD A, (HL)      ; A = ARRAY[0]
        LD (MAX), A     ; MAX = ARRAY[0]
        INC HL
        LD B, 4          ; 4 remaining comparisons
LOOP    LD A, (HL)      ; A = the next candidate — register-indirect (cpu8bit1-7)
        CALL UPDATE_MAX ; NEW — call the subroutine (real stack use, cpu8bit1-7)
        INC HL
        DJNZ LOOP       ; cpu8bit1-8
DONE    JR DONE

; --- Subroutine: UPDATE_MAX ---
; Input: A = candidate. Updates MAX in place if the candidate is bigger.
UPDATE_MAX
        LD C, A         ; save the candidate in C — NOT B, which DJNZ's own loop still needs
        LD A, (MAX)
        CP C            ; NEW — compare A (MAX) against C (candidate)
        JR NC, SKIP     ; NEW — jump if No Carry (MAX >= candidate)
        LD A, C
        LD (MAX), A
SKIP    RET            ; NEW — return, pulling the address CALL pushed

ARRAY   DEFB 10,50,30,80,20
MAX     DEFB 0

New here: CP (compares A against a value, like CMP on the 6502), JR NC (jump if no carry), and — for the first time on this side too — CALL/RET, the Z80's own subroutine call, using its fully flexible 16-bit stack from cpu8bit1-7.

The Real Payoff: Two Opposite Flag Conventions

Both subroutines do the same comparison — yet the 6502's CMP/BCC and the Z80's CP/JR NC read the Carry flag in opposite directions:

On the 6502, Carry set means "no borrow was needed" — the first value was large enough. On the Z80, Carry set means the exact opposite — "a borrow was needed," meaning the first value was too small. Anyone porting comparison logic between the two chips has to consciously flip this reading, or the ported code will silently do the wrong thing while looking completely correct on the page. It's a small, precise, entirely real example of exactly the kind of "same-looking operation, genuinely different behavior" this whole course has been surfacing since cpu8bit1-1.

Chapter Attribution

Hands-On Exercises