Exercise 2: How IM 2's Vector Address Is Assembled — Possible Solution
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ASSEMBLING THE 16-BIT VECTOR ADDRESS
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Per this chapter's own explanation, IM 2's final vector address is
built from two separate pieces, one from each side of the interrupt:

  High byte: taken directly from the I register — a dedicated
             register the programmer loads in advance with the high
             byte of wherever the handler-address table lives in
             memory.

  Low byte:  supplied by the interrupting DEVICE itself, at the exact
             moment the interrupt occurs — not fixed in advance by
             the programmer, but determined by whichever specific
             piece of hardware is requesting attention right now.

Combined together (I register's value as the high byte, device-
supplied value as the low byte), these two bytes form one complete
16-bit address. The CPU doesn't jump directly to THAT address, though
— it treats that address as a POINTER, and reads the actual two-byte
handler address stored there, then jumps to that.

WHY THIS ALLOWS UP TO 128 DISTINCT HANDLERS
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Because the low byte comes from the interrupting device rather than
being fixed by the CPU, DIFFERENT devices can supply DIFFERENT low
bytes, each one pointing at a different location within the table the
I register's high byte establishes. Per this chapter's own note, the
device-supplied byte is even, which means each entry in the table
naturally occupies 2 bytes (one full address) without ever landing on
an odd address — and with a full byte's worth of possible even values
(0, 2, 4, ... up to 254), that works out to up to 128 distinct
2-byte table slots, each one able to hold a completely different
handler address.

WHY THIS BEATS ONE SHARED ENTRY POINT
------------------------------
Contrast this with the 6502's own IRQ vector (this chapter's own
comparison table) — every device that can trigger an IRQ lands at the
exact SAME single handler address, meaning that shared handler has to
contain its own logic to figure out, after the fact, which device
actually caused the interrupt. With IM 2, that dispatch work is done
automatically by the hardware itself, before the handler even starts
running — each device's own supplied low byte routes it straight to
its own dedicated handler, with no need for the handler to first
figure out who called it.

WHY THIS WORKS AS AN ANSWER
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It explains precisely which byte comes from where (I register =
high byte, device = low byte), correctly identifies the extra
indirection step (the combined address is a pointer to the real
handler address, not the handler address itself), and explains the
128-handler figure using the chapter's own even-byte detail, then
contrasts the result directly against the 6502's single shared vector.