6502 Registers and the Stack

cpu8bit1-2 named A, X, and Y as the 6502's general-purpose registers, and left the rest for here. This chapter completes the picture — the special-purpose registers that make the chip actually work (PC, SP, P), a real hardware stack that's genuinely better than assembly1-7's manual LC-3 approach in one way and more limited in another, and the concrete reason the small register file forces the addressing-mode cleverness cpu8bit1-4 covers next.

The Full 6502 Register Set

The Status Register — Richer Than N/Z/P

assembly1-4's N/Z/P condition codes were LC-3's own deliberately simplified teaching version of a real status register. The 6502's actual P register packs eight individual flag bits, several of which LC-3 simply never needed:

• N (Negative) and Z (Zero) — direct counterparts to two of LC-3's own three condition codes.
• C (Carry) — LC-3 never had one, because LC-3's registers were a full 16 bits wide, matching its own word size, so ordinary addition never needed to signal "this overflowed the register." The 6502's 8-bit registers make Carry essential — see below.
• V (Overflow) — a separate flag specifically for signed overflow, distinct from Carry's unsigned overflow signal — a distinction LC-3's simplified model never had to draw.
• D (Decimal mode) — switches addition/subtraction into binary-coded decimal, useful for real-world calculations (early point-of-sale and calculator-style applications) where exact decimal results matter more than raw binary speed.
• I (Interrupt disable) — a real hardware feature LC-3 never modeled at all.
• B — only meaningful in the copy of P pushed to the stack during an interrupt, distinguishing a software-triggered BRK from a real hardware interrupt.

Why the Carry Flag Matters So Much Here

The 6502 is an 8-bit CPU — its registers and internal data paths handle one byte (0–255) at a time — but its address bus is 16 bits, giving it a full 64KB address space. That split matters: any arithmetic on a number bigger than 255 has to be built by hand, one byte at a time, chaining the result of one 8-bit addition into the next using Carry:

CLC              ; clear Carry before starting a multi-byte add
LDA NUM1_LOW
ADC NUM2_LOW    ; add with carry — low bytes
STA RESULT_LOW
LDA NUM1_HIGH
ADC NUM2_HIGH   ; carry from the low-byte add feeds into this one
STA RESULT_HIGH

LC-3's own 16-bit-wide registers meant a value never needed to be split across two registers just to add it — this entire pattern, and the Carry flag it depends on, simply had no reason to exist in assembly1. It's a direct, concrete consequence of the 6502 being genuinely 8-bit in a way LC-3, built purely for teaching, never was.

The Stack — Real Hardware, Genuinely Constrained

assembly1-7 had to build PUSH and POP entirely out of ordinary ADD/STR/LDR instructions, because LC-3 provides no dedicated stack-pointer register at all. The 6502 is a real improvement here: SP is a genuine, dedicated hardware register, and the chip provides native push/pull instructions:

PHA   ; push the accumulator onto the stack
PLA   ; pull the top of the stack back into the accumulator
PHP   ; push the status register
PLP   ; pull the status register back

Compare that single PHA against assembly1-7's own multi-instruction manual push sequence — this is real, dedicated hardware doing in one instruction what LC-3 needed three for.

The constraint: SP is only 8 bits wide, not 16. It doesn't hold a full address — it holds just the low byte of one, and the high byte is permanently fixed to $01 by the hardware. This locks the entire stack to a single 256-byte region, page 1 (addresses $0100–$01FF), no matter what. The stack grows downward — SP decrements on every push, increments on every pull — the same downward-growing convention assembly1-7's own example already used.

Why So Few Registers Forced Clever Addressing

Three general-purpose registers — A, X, Y — is genuinely little working space. Adding more wasn't an option without breaking cpu8bit1-2's own transistor budget. Instead, the 6502's designers found a different way to get fast, flexible access to values without paying for more physical registers: a special, quick-access region of memory that instructions can reach with shorter encodings than ordinary memory access requires. cpu8bit1-4 covers this technique — zero-page addressing — in full, as the chip's real answer to "we can't afford more registers."

Hands-On Exercises