6502 Addressing Modes — Zero Page as "Extra Registers"

cpu8bit1-3 closed with a promise: with only three general-purpose registers, the 6502 needed another way to get fast, flexible access to values. This chapter delivers on it — zero page, the chip's real, concrete answer to a transistor budget that couldn't afford more registers, plus the rest of the addressing modes that make real 6502 programs practical.

Zero Page — The Chip's Real Answer

Addresses $0000–$00FF — the first 256 bytes of memory — get special treatment on the 6502. Because every address in that range fits in a single byte, an instruction accessing zero page only needs to encode one address byte instead of two. That shorter encoding means less to fetch and fewer internal cycles to compute the effective address — zero page is measurably faster than ordinary memory access, not just shorter to type.

The practical effect: with 256 available slots, zero page behaves like a bank of pseudo-registers, vastly larger than the 3 real ones (A, X, Y) the chip actually has — at a real cost (an extra memory access instead of a truly free register read), but a far smaller cost than physical registers would have added to the transistor budget cpu8bit1-2 already established as the chip's central constraint.

Absolute Addressing — Reaching the Full 64KB

Absolute addressing embeds a full, two-byte address directly in the instruction, reaching anywhere across the 6502's entire 64KB space. This is worth contrasting directly with assembly1-3's own PC-relative LD: LC-3 had to compute an address from an offset specifically because its instructions were a fixed 16 bits wide, with no room left over for a full standalone address. The 6502 doesn't have that problem — its instructions are variable length (1 to 3 bytes), so a full 2-byte address simply costs one extra byte in the instruction stream, not a fight for bits within a single fixed-width word.

LDA $0050    ; zero page — 2 bytes, address fits in one byte
LDA $1050    ; absolute — 3 bytes, a full two-byte address

Indexed Addressing — Zero Page,X and Absolute,X/Y

Adding X or Y to a base address turns either mode into an indexed one — the mechanism behind iterating over an array, with the index register playing a role similar to assembly1-3's own base+offset LDR, except the "offset" here is a whole register that changes every loop iteration rather than a fixed 6-bit constant baked into the instruction.

LDA $0050,X   ; zero page,X — base $0050 plus X
LDA $1050,X   ; absolute,X — base $1050 plus X, reaches the full 64KB

(Zero Page),Y — Indirect-Indexed: A Real Pointer Dereference

This is the 6502's most powerful addressing mode, and the direct answer to a problem assembly1-3's own indirect mode (LDI/STI) never fully solved: accessing an array whose starting address isn't known until the program actually runs.

A zero-page location holds a full 16-bit pointer — the low byte at the zero-page address itself, the high byte at the next one over. (zp),Y reads that pointer, then adds Y to the pointer's value to get the final effective address:

; zero page $10/$11 holds a pointer to $3000
LDA #$00
STA $10        ; low byte of the pointer
LDA #$30
STA $11        ; high byte of the pointer — together, $10/$11 hold $3000

LDY #$00
LDA ($10),Y   ; reads from $3000 + Y — a real runtime pointer dereference

This is genuinely more capable than LC-3's own LDI, which could follow a pointer but never combine that with an index in the same instruction. (zp),Y does both at once — exactly what's needed to walk through an array whose address is only known at runtime.

A related, less commonly needed mode, (zero page,X) — indexed-indirect — works the other way around: X is added to the zero-page address first (wrapping within zero page, the same way zp,X does), and whatever pointer sits at the resulting location is used directly, with no further offset. It shows up most often selecting between several fixed pointers — a jump table, for instance — rather than walking through an array.

Real Cycle-Cost Comparison

Zero page's own 3-cycle cost against absolute's 4 is the concrete, measurable version of "extra registers" this chapter opened with — a real, repeatable speed advantage for any value accessed often enough to be worth keeping in the first 256 bytes.

Hands-On Exercises