Digital Logic Basics

Basic Electronics

Course 1 · Chapter 8 · Digital Logic Basics

Chapter 7 dealt with signals that can take any voltage. This chapter is about the opposite: signals that are deliberately only ever one of two things, LOW or HIGH, 0 or 1. Everything inside a microcontroller works this way, and so do the small logic chips that sit around it on a robot: chips that combine switch signals, remember a button press, count wheel pulses, turn three pins into sixteen, or time a pulse with no program at all. A digital signal is tough: noise smaller than the gap between the two levels vanishes without trace, which is why a computer can copy a file perfectly while a tape cannot. The chapter uses the divider and pull-up ideas of Basic Electronics 3, the RC timing of Basic Electronics 4, the transistor switch of Basic Electronics 6 and the comparator with hysteresis of Basic Electronics 7. The mathematics of logic (Boolean algebra, simplification, adders) is a separate course, Boolean Algebra & Digital Logic; here we look at the electrical side: voltages, currents, chips and wiring.

1. Logic levels and noise margins

A digital input does not compare against exactly 2.5 V. Each chip family guarantees that a voltage below VIL is read as LOW, a voltage above VIH is read as HIGH, and that anything in between is undefined (it may read either, or oscillate). A driving output guarantees the opposite promise: its LOW is at most VOL and its HIGH is at least VOH, when supplying the rated current. For two chips to talk, the output's promise must fit inside the input's requirement; the room left over is the noise margin.

VIL = highest voltage an input still reads as LOW VIH = lowest voltage an input reads as HIGH VOL = highest voltage an output gives for LOW VOH = lowest voltage an output gives for HIGH Noise margin, LOW : NML = VIL - VOL (how much noise a LOW can pick up before it might be misread) Noise margin, HIGH : NMH = VOH - VIH Both must be positive for the connection to work at all. A negative number means a guaranteed failure. Voltage levels on one wire (5 V CMOS, 74HC): 5.0 V --------------------------------- supply 4.4 V --------------------------------- VOH (an output HIGH is at least this) NMH = 0.9 V 3.5 V --------------------------------- VIH (an input reads HIGH above this) undefined region 1.5 V --------------------------------- VIL (an input reads LOW below this) NML = 1.4 V 0.1 V --------------------------------- VOL (an output LOW is at most this) 0.0 V --------------------------------- ground
Family / pinSupplyVIL maxVIH minVOL maxVOH minNMLNMH
74LS (old TTL)5 V0.8 V2.0 V0.5 V2.7 V0.3 V0.7 V
74HC (CMOS)5 V1.5 V (0.3 VCC)3.5 V (0.7 VCC)0.1 V4.4 V1.4 V0.9 V
74HCT (CMOS, TTL inputs)5 V0.8 V2.0 V0.1 V4.4 V0.7 V2.4 V
74HC (CMOS)3.3 V0.99 V2.31 V0.1 V3.2 V0.89 V0.89 V
LVTTL (3.3 V logic, 74LVC)3.3 V0.8 V2.0 V0.4 V2.4 V0.4 V0.4 V
ESP32 GPIO pin3.3 V0.825 V (0.25 VDD)2.475 V (0.75 VDD)0.33 V (0.1 VDD)2.64 V (0.8 VDD)0.50 V0.17 V
ATmega328P pin (Uno, Nano), input only5 V1.5 V (0.3 VCC)3.0 V (0.6 VCC)————

These figures are typical datasheet values at light load (74HC outputs quoted at 20 µA; at 4 mA, VOL rises to about 0.26 V and VOH falls to about 3.8 V). The datasheet of the exact part is the authority; the method is what matters.

Checking a connection: the two inequalities

A driver output can feed a receiver input only if VOH(driver) >= VIH(receiver) AND VOL(driver) <= VIL(receiver) and the output voltage never exceeds what the input tolerates (usually VCC + 0.3 V). Worked examples: 74LS output to a 74HC input (both 5 V): VOH = 2.7 V is below VIH = 3.5 V FAILS (the reason 74HCT chips exist) 74HC (5 V) to a 74LS input: 4.4 V > 2.0 V and 0.1 V < 0.8 V works ESP32 pin (3.3 V) to a 74HC at 5 V: VOH = 2.64 V is below VIH = 3.5 V FAILS ESP32 pin to a 74HCT at 5 V: 2.64 V > 2.0 V, NMH = 0.64 V; 0.33 V < 0.8 V works (use a 74HCT, or run the chip at 3.3 V) 74HC at 5 V to an ESP32 pin: 4.4 V is more than 3.3 V + 0.3 V = 3.6 V DAMAGES the pin (section 10) 74HC at 3.3 V to an ESP32 pin: VOH about 2.9 V (at 4 mA) is above VIH = 2.475 V works
Why the noise margin is not a spare "extra"
The margin has to cover everything that gets onto the wire: the ground-voltage difference between two boards, crosstalk from a neighbouring wire, and the supply ripple of Basic Electronics 7. Half a volt sounds ample until a motor starts on the same ground wire. A margin that is only 0.17 V (the ESP32 HIGH into a 2.475 V threshold) works on the bench and fails on the robot; the cure is a shorter wire, a better ground or a buffer chip.

2. Gates and truth tables

A gate is the smallest logic circuit: one output that is a fixed function of one or two inputs. The function is written as a truth table, which lists the output for every input combination (Boolean Algebra & Digital Logic 2 covers the operators and truth tables in depth; Boolean Algebra & Digital Logic 6 covers gates and how to combine them). The six you need every day:

ABANDORNANDNORXORXNORNOT A
000011011
010110101
100110100
111100010
GateIn wordsExpression74HC chip (4 or 6 gates)A robot use
NOT (inverter)Output is the opposite of the inputY = Ā (A with a bar)74HC04 (6)Turn an active-low sensor into an active-high signal
ANDOutput HIGH only if both inputs are HIGHY = A · B74HC08 (4)Run the motor only if the enable switch AND the bumper-clear signal are both true
ORHIGH if either input is HIGHY = A + B74HC32 (4)Stop if the left OR the right bumper is hit
NANDThe opposite of AND: LOW only if both inputs are HIGHY = (A · B)̄74HC00 (4)The universal building block (below); also latches
NORThe opposite of OR: HIGH only if both inputs are LOWY = (A + B)̄74HC02 (4; its pins differ)“Nothing detected”: HIGH when all sensors are quiet
XORHIGH if the inputs differY = A ⊕ B74HC86 (4)Compare two bits; the heart of an adder; detect that two switches disagree

Bubbles, bars and active-low names

A small circle on a gate symbol means inversion; a bar over a signal name (or a trailing # or _N or n) means active low: the signal does its job when it is LOW. A chip's CS̄ (chip select), RESET̄ and OĒ (output enable) are almost always active low, because open-drain wiring (section 5) and old TTL both pull more strongly low than high. When reading a datasheet, the name tells you which level means “yes”.

Why NAND is called universal

Any logic function can be built from AND, OR and NOT. A NAND gate can make all three, so a pile of NAND gates (a single 74HC00 holds four) can build any logic circuit; NOR has the same property. This is why chips and old computers were designed around one gate type.

Using only NAND gates (N(a, b) means NAND of a and b) NOT A = N(A, A) tie the two inputs together: 1 gate AND = N( N(A,B), N(A,B) ) a NAND followed by a NOT: 2 gates OR = N( N(A,A), N(B,B) ) invert both inputs, then NAND: 3 gates XOR = N( N(A, M), N(B, M) ) with M = N(A, B) 4 gates, exactly one 74HC00 Why OR works (De Morgan's law, Boolean Algebra & Digital Logic 3): NOT( NOT(A) AND NOT(B) ) = A OR B Check the XOR for A = 1, B = 0: M = N(1,0) = 1; N(A,M) = N(1,1) = 0; N(B,M) = N(0,1) = 1; N(0,1) = 1 = 1 XOR 0 correct Check A = 1, B = 1: M = N(1,1) = 0; N(1,0) = 1; N(1,0) = 1; N(1,1) = 0 = 1 XOR 1 correct

3. Gates from transistors

A gate is only a few switches. Chapter 6 showed that a transistor is a switch that a voltage on its input can turn on or off; a logic gate is transistors arranged so that the output is pulled to LOW or HIGH by the right input combination.

Discrete NPN gates

The first logic circuits used bipolar transistors and resistors. With one NPN transistor and a pull-up resistor you have a NOT gate (input HIGH: transistor on, output pulled LOW; input LOW: transistor off, the resistor pulls the output HIGH). Put two transistors in parallel and the output goes LOW if either is on: a NOR. Put them in series and the output goes LOW only if both are on: a NAND. Build 1 builds the NAND.

NOR: two NPNs in PARALLEL (Rc = collector pull-up resistor; B, C, E = base, collector, emitter) +5 V o------+ | [ Rc ] | +------------+---------------o Y | | C C A o-[ R ]-B Q1 B Q2 -[ R ]-o B E E | | +-----+------+ | 0 V o-------------+ Either transistor, when on, pulls Y LOW. Y is HIGH only if A and B are both LOW. (NOR) NAND: two NPNs in SERIES (this is Build 1) +5 V o------+ | [ Rc ] | +----------------o Y | C A o-[ R ]-B Q1 E | C B o-[ R ]-B Q2 E | 0 V o-------+ Y falls only when BOTH transistors conduct. Y is LOW only if A and B are both HIGH. (NAND)

Why this was replaced: the resistor conducts the whole time the output is LOW. With Rc = 1 kΩ on 5 V, that is (5 − 0.2)/1 kΩ = 4.8 mA per gate while LOW, so 100 gates draw half an ampere. A discrete gate also has a weak HIGH (it relies on a resistor that is slow when it must charge a wire's capacitance) and a switching threshold of about 0.7 V (one base-emitter drop), so noise margins are poor.

CMOS: complementary MOSFETs

Modern logic (the 74HC family and everything inside a microcontroller) uses pairs of MOSFETs, one P-channel device that conducts when its gate is LOW and one N-channel that conducts when its gate is HIGH. Wired complementary, one is always off:

CMOS NOT: CMOS NAND, two inputs: Vcc o---+ Vcc o---------+-----------+ | | | [ P-ch ] gate = A [ P-ch A ] [ P-ch B ] two P-channels in PARALLEL | | | +------o Y +-----+-----+ | | [ N-ch ] gate = A +-----------o Y | | 0 V o---+ [ N-ch A ] two N-channels in SERIES | A = 0: P on, N off: Y = Vcc (HIGH) [ N-ch B ] A = 1: P off, N on: Y = 0 V (LOW) | 0 V o-------+ gates: P-ch A and N-ch A are driven by A; P-ch B and N-ch B are driven by B. A = B = 1: both N on, both P off: Y = LOW. Any input LOW: that P is on, a series N is off: Y = HIGH. (NAND)
PropertyResistor-transistor gateCMOS gate (74HC)
Current when sitting stillMilliamps while the output is LOWNanoamps: one transistor of each pair is always off, so no path from Vcc to ground
Output HIGHThrough a resistor: weak, slowThrough a P-channel switch: strong, equal to the LOW
Input thresholdAbout 0.7 V, not adjustableAbout half the supply (2.5 V at 5 V): symmetrical noise margins
Input currentBase current (hundreds of µA)About 1 µA leakage (a MOSFET gate is insulated): one output can drive dozens of inputs
WeaknessPower wasteDraws current only when switching, so power rises with frequency (below); static electricity can punch through the gate oxide
Dynamic power of a CMOS gate: P = Cpd x Vcc^2 x f + the power spent charging the load: C(load) x Vcc^2 x f Cpd = the chip's "power dissipation capacitance" from the datasheet (about 20 pF per gate for a 74HC00) Example: one gate, 5 V, 1 MHz: P = 20e-12 x 5^2 x 1e6 = 0.5 mW (current 0.1 mA) Example: the same gate at 10 MHz = 5 mW: 10 times the frequency, 10 times the power Example: at 3.3 V, 1 MHz: P = 20e-12 x 3.3^2 x 1e6 = 0.22 mW (power goes with the SQUARE of the supply: why low-voltage chips run cool) Compare 74LS: about 2 mW per gate at ANY frequency, even when idle.

4. Using the 74HC series

The 74HC chips are the standard small logic parts for hobby work: cheap, widely available in DIP (breadboard) packages, and with a supply range of 2 V to 6 V, so one chip serves a 5 V Arduino and a 3.3 V Pico. The 74HC chips are numbered by function (74HC00 is four NAND gates whichever maker sells it). Pinouts follow a pattern: the supply on the top corner, ground on the bottom corner, gate inputs and outputs in order. Read the datasheet before wiring a chip you have not used (the 74HC02 NOR chip, for example, puts the output first on each gate).

74HC00 (four NAND gates) and 74HC08 (AND), 74HC32 (OR), 74HC86 (XOR) all share this DIP-14 pinout, seen from above, notch at the left: pin 14 VCC 13 4B 12 4A 11 4Y 10 3B 9 3A 8 3Y (top row, right to left on the chip) pin 1 1A 2 1B 3 1Y 4 2A 5 2B 6 2Y 7 GND (bottom row, left to right) Gate 1: inputs 1A, 1B (pins 1, 2), output 1Y (pin 3). Gate 2: pins 4, 5 -> 6. Gate 3: pins 9, 10 -> 8. Gate 4: pins 12, 13 -> 11. 74HC04 and 74HC14 (six inverters) use the same power pins: 1A 1, 1Y 2, 2A 3, 2Y 4, 3A 5, 3Y 6, GND 7, 4Y 8, 4A 9, 5Y 10, 5A 11, 6Y 12, 6A 13, VCC 14.

The rules that keep a 74HC chip working

  • Never leave an input floating. A CMOS input has almost no leakage, so an unconnected pin floats to a random voltage picked up from the air (50 Hz hum, your hand), sits near the switching threshold where both transistors conduct (the chip then draws extra supply current and may get warm), and the output chatters. Tie every unused input to GND or VCC, and tie unused gates' inputs too (an unused gate is a gate with an unconnected input). Leave unused outputs unconnected.
  • Decouple every chip: 100 nF ceramic across VCC and GND, as close to the chip's pins as the breadboard allows (Basic Electronics 4). When all the output transistors switch together, they pull a brief spike of current. Without the capacitor the spike drops the supply voltage by tens of millivolts or more, and other chips glitch.
  • Respect the supply range. 74HC chips run from 2 to 6 V and are damaged above about 7 V. 74HCT is 4.5 to 5.5 V only. A 74HC chip powered from 3.3 V will not understand a 5 V input and may be destroyed by it (section 10).
  • Never tie two normal outputs together. If one drives HIGH and another LOW the two outputs fight: the current is about 5 V / (60 Ω + 60 Ω) = 40 mA, which exceeds the rating and can destroy both. Where several devices must share one wire, use open-drain outputs (section 5) or a tri-state bus.
  • Keep input edges fast. A plain 74HC input needs the voltage to cross the threshold quickly (the datasheet specifies a rise time of 500 ns or less at 4.5 V). A slow edge, such as the output of an RC network or a human-speed switch, lingers in the undefined region and gives multiple output pulses; this is the job of the Schmitt-trigger chips in section 6.

Fan-out and propagation delay

Fan-out = how many inputs one output can drive. For CMOS-to-CMOS the DC current is only about 1 uA per input, so the limit is SPEED: each input adds about 3.5 pF to the output's load; the wire adds about 10 pF per 10 cm. An output works as a resistor of about Rout = VOL / IOL = 0.26 V / 4 mA = 65 ohm (74HC, 5 V, from the datasheet's 4 mA point). It must charge the load capacitance, so the extra delay is about t = 0.69 x Rout x C(load) Example: one output drives 10 inputs plus 10 cm of wire: C = 10 pF + 10 x 3.5 pF = 45 pF extra delay = 0.69 x 65 ohm x 45 pF = 2.0 ns (tiny: ten inputs is a perfectly fine load) A long ribbon cable of 200 pF would give 0.69 x 65 x 200 pF = 9.0 ns: that is when you buffer. Propagation delay tpd = the time from an input crossing its threshold to the output crossing its threshold. 74HC00 at 5 V: about 8 to 10 ns typical; at 3.3 V: about 12 to 16 ns (the lower supply lowers the drive) The delay limits the speed and gives hazards: when a signal takes two paths of different length (say 10 ns and 20 ns), the output may flicker briefly ("glitch") before it settles. Inputs that change one at a time are safe; a clock must go through the SAME number of gates as its data, or use a flip-flop (section 7), which samples at an instant. Example, a ring oscillator: three inverters in a loop (Y of the last goes back to the first). Each edge goes round the loop twice per cycle: period = 2 x 3 x 10 ns = 60 ns f = 1 / 60 ns = 16.7 MHz (an odd number of inverters is needed; an even number just latches)
FamilySupplyInput thresholdsTypical delayOutput drive (rated)Use
74HC2 to 6 V0.3 and 0.7 of VCC8 ns at 5 V±4 mAThe general choice; 3.3 V and 5 V projects
74HCT4.5 to 5.5 VTTL: 0.8 V and 2.0 V10 ns±4 mAA 5 V chip that reads 3.3 V signals (a one-chip level shifter, up only)
74AHC / 74AHCT2 to 5.5 Vas HC / as HCT4 to 5 ns±8 mAFaster HC / HCT replacement; LED-strip level shifting (74AHCT125)
74LVC1.65 to 3.6 VLVTTL, inputs tolerate 5.5 V3 to 5 ns±24 mA3.3 V logic that is safe to feed from 5 V (down-shifting)
74LS5 V onlyTTL10 ns4 to 8 mA lowOld, power-hungry; look-alike parts in old kits
CD40003 to 15 V0.3 and 0.7 of VCC50 to 100 ns at 5 Vabout 1 mASlow, but runs directly from a 9 V or 12 V battery

Typical figures; the datasheet of each part decides.

5. Pull-ups, pull-downs and open-drain outputs

Floating inputs and the switch

Basic Electronics 3 introduced the pull-up and pull-down resistor. It exists because a switch connects an input to only one of the two levels. With a button between the input and ground and nothing else, the input floats when the button is released. A 10 kΩ pull-up resistor to VCC supplies the other level:

Pull-up (the usual way, buttons to ground): Pull-down (buttons to VCC): +5 V o----+ +5 V o----+ | | [ R 10 k ] [ SW ] | | +------o to the input +------o to the input | | [ SW ] [ R 10 k ] | | 0 V o-----+ 0 V o---+ Released: no current in R (input draws about 1 uA), so the input sits at 5 V - 10 k x 1 uA = 4.99 V, a clean HIGH. Pressed: the input is 0 V and the resistor wastes I = 5 V / 10 k = 0.5 mA only while pressed. (pull-ups are the convention; the button reads 0 when pressed: active low) Choosing R: too small wastes current when pressed; too large makes the HIGH level slow, noisy or leaky. Rise time of the node = 2.2 x R x C (10 % to 90 %) C = input + wire, 20 pF: 2.2 x 10 k x 20 pF = 0.44 us (fine) A long wire of 500 pF (a bumper switch on the end of a cable): 2.2 x 10 k x 500 pF = 11 us; use 2.2 k for more noise immunity: 2.3 mA when pressed. Microcontroller boards have internal pull-ups of 20 to 50 k (INPUT_PULLUP in Arduino code), enough for a button but weak on a long cable.

Open-drain and open-collector outputs

A normal (totem-pole or push-pull) output has two switches: it drives HIGH and LOW. An open-drain output (MOSFET, as in 74HC03 or an I2C pin) or open-collector output (bipolar, as in an LM393 comparator, from Basic Electronics 7) has only the lower switch: it can pull the wire to ground or let go, and a pull-up resistor to a supply does the HIGH. Because the output cannot actively drive HIGH, many open-drain outputs can safely share one wire:

+5 V o-----+ | [ Rp 3.3 k ] A B wire | 0 0 0 (0 = that output is pulling LOW) +----------+----------+----o 0 1 0 (1 = that output has let go) | | | 1 0 0 [ out A ] [ out B ] [ out C ] 1 1 1 | | | 0 V o------+----------+----------+ The wire is HIGH only if EVERY output lets go, so the wire = A AND B AND C: a "wired-AND". Read it as active-low: the wire goes LOW when ANY device pulls it low. One pin can thus watch several bumper sensors, or an "interrupt" line shared by many chips, and I2C's SDA and SCL lines work exactly this way, which also allows two devices to share the bus without a collision. Choosing the pull-up Rp (5 V, wire capacitance 200 pF, each output can sink IOL = 3 mA at VOL = 0.4 V): Lower limit: the output must be able to hold the wire LOW against the pull-up: Rp(min) = (Vcc - VOL) / IOL = (5 - 0.4) / 3 mA = 1.53 k Upper limit: the wire must rise fast enough: rise time from 30 % to 70 % of Vcc t = 0.8473 x Rp x C (the I2C spec's formula) for t at most 1 us (I2C at 100 kHz): Rp(max) = 1 us / (0.8473 x 200 pF) = 5.9 k Choose 3.3 k: t = 0.8473 x 3.3 k x 200 pF = 0.56 us current when pulled low = 4.6 V / 3.3 k = 1.4 mA
Open-drain also gives you free level shifting
Because an open-drain output only pulls to ground, the pull-up can go to any voltage that the receiving chip accepts: pull the same wire up to 3.3 V for a 3.3 V board or to 5 V for a 5 V board. Section 10 uses a MOSFET to make this work in both directions.

6. Schmitt-trigger inputs and debouncing

Basic Electronics 7 added hysteresis to a comparator with a resistor from output to input. A Schmitt-trigger input builds the same idea into a logic gate: the input has two thresholds, VT+ for a rising signal and VT− for a falling one. Once the output has switched, the input must travel the whole gap back before it switches again, so a slow or noisy edge produces one clean transition. The 74HC14 is a hex inverter with Schmitt inputs; 74HC132 is the NAND version.

74HC14 at 5 V, typical: VT+ = 2.4 V (rising), VT- = 1.4 V (falling), hysteresis = 1.0 V (datasheet gives min and max: VT+ between 1.9 and 3.15 V) Example: a slow input ramps from 0 V to 5 V with 0.5 V of noise riding on it. Plain 74HC04 (one threshold, about 2.5 V): the noise crosses 2.5 V several times, so the output gives several pulses. 74HC14: the output switches once when the input rises past 2.4 V, and cannot switch back until the input falls below 1.4 V. Noise of 0.5 V cannot bridge the 1.0 V gap, so there is exactly one clean edge. (The output is the inverse of the input.) Use it for: a slow RC signal (below), a push button, a sensor with a slowly changing output, cleaning up a long wire, a simple oscillator (an RC around one gate).

Debouncing

A mechanical switch does not close cleanly. The contacts bounce, making and breaking for 1 to 10 ms (sometimes 20 ms) and producing a burst of pulses that a fast chip counts as many presses. Three cures:

  1. Software: ignore further changes for about 20 ms after the first one. Free, and usual with a microcontroller.
  2. RC filter plus a Schmitt gate (Basic Electronics 4 used the RC; here is the gate that makes it work):
+5 V o-----+ | [ R 10 k ] | +----------+------------+----o to 74HC14 pin 1 (1A); output 1Y (pin 2) is the clean, INVERTED signal | | | [ SW ] [ C 1 uF ] (the node N) | | [ Rs 100 ] | | | 0 V o------+----------+ Switch released: C charges through R toward 5 V. Time to reach VT+ = 2.4 V: t = - R C ln( 1 - VT+/Vcc ) t = - 10 k x 1 uF x ln( 1 - 2.4/5 ) = 10 ms x 0.654 = 6.5 ms (with C = 100 nF: 0.65 ms; with 10 uF: 65 ms) Switch pressed: C discharges through Rs (100 ohm) in t = - Rs C ln( VT-/Vcc ) = 100 x 1 uF x ln(5/1.4) = 0.13 ms peak current 5 V / 100 ohm = 50 mA A bounce during release lets C charge only while the contacts are open. A gap of 1 ms charges it to 5 x (1 - e^(-1 ms/10 ms)) = 0.48 V, far below VT+, and the next closure discharges it again: the output never moves. The delay is the price: 6.5 ms after the switch opens. Rs is optional; it limits the discharge current through the switch contacts.
  1. A latch with a two-way (changeover, SPDT) switch: the first contact closing sets the latch, and bounce on the same contact changes nothing. See the SR latch in section 7. This is how the earliest hardware did it, and it needs no timing at all.

7. Latches and flip-flops: one bit of memory

All the circuits so far are combinational: the output depends only on the inputs now. A sequential circuit remembers: its output depends on what happened before. The smallest memory is two gates that feed each other (Boolean Algebra & Digital Logic 8 builds flip-flops and memory in logic terms).

The SR latch

Two NAND gates, each output fed into the other gate's input (a 74HC00; the inputs are active LOW): gate 1: Q = NAND( S-bar, Q-bar ) inputs: S-bar and the output of gate 2 gate 2: Q-bar = NAND( R-bar, Q ) inputs: R-bar and the output of gate 1 (draw it as two NAND symbols one above the other; the output of each runs back, crossing the other's wire, to one input of the other gate) S-bar R-bar | Q Q-bar | What happens 1 1 | holds holds | Remembers the last state 0 1 | 1 0 | SET: Q goes to 1 1 0 | 0 1 | RESET: Q goes to 0 0 0 | 1 1 | Not allowed: both outputs HIGH; on releasing both together the result is unpredictable (a race) Why it remembers: with both inputs HIGH, each NAND acts as an inverter of the other output, a loop of two inversions that holds either state forever. Pin wiring on a 74HC00: S-bar -> pin 1 (1A); Q-bar (pin 6) -> pin 2 (1B); output Q = pin 3 (1Y). R-bar -> pin 4 (2A); Q (pin 3) -> pin 5 (2B); output Q-bar = pin 6 (2Y). Inputs held HIGH by 10 k pull-ups to VCC.

With a changeover switch joined to ground, one throw to S̄ and the other to R̄ (each with its pull-up), the latch is a perfect debouncer: the first touch of a contact flips it and the later bounce changes nothing, because the other contact is already open and the first can only re-assert what it has set.

The D flip-flop and the 74HC74

A latch changes whenever its inputs do. A flip-flop samples its input only at an instant: the rising edge of a clock input. The D flip-flop is the commonest: on each rising clock edge, Q takes the value that D has at that moment, and keeps it until the next edge. Because the output changes at one instant, everything driven by the same clock changes together, and the glitches of section 4 are filtered out.

74HC74: two D flip-flops, DIP-14, notch at the left, pins numbered anticlockwise from pin 1 at the bottom-left. pin 14 VCC 13 2RD-bar 12 2D 11 2CP 10 2SD-bar 9 2Q 8 2Q-bar (top row) pin 1 1RD-bar 2 1D 3 1CP 4 1SD-bar 5 1Q 6 1Q-bar 7 GND (bottom row) D = data; CP = clock (rising edge); SD-bar = asynchronous SET (active low); RD-bar = asynchronous RESET (active low). The SET and RESET inputs act at once and override the clock: tie both HIGH (to VCC) when not used, and never leave them floating. On each rising edge of CP: Q becomes D; Q-bar is its opposite. Timing: setup time tsu = D must be steady this long BEFORE the clock edge (about 20 ns for a 74HC74 at 4.5 V) hold time th = D must stay steady this long AFTER the edge (about 0 to 5 ns) clock-to-output delay tpd about 15 ns; maximum clock frequency: tens of MHz. Violate setup or hold and the flip-flop may land half-way and take a long time to settle: METASTABILITY. This is why a signal that arrives at random times, like a button, is re-timed through two flip-flops in a row before the logic uses it.

Toggle: divide a frequency by two

Connect Q-bar back to D. At each rising clock edge, Q takes the value of D = the OLD Q-bar, so Q flips every time: clock rising edge number: 1 2 3 4 5 6 ... Q after that edge: 1 0 1 0 1 0 ... (starting from Q = 0) Q makes one full cycle (HIGH then LOW) for every TWO clock cycles: f(Q) = f(clock) / 2, with exactly 50 % duty Chain n toggle stages (Q of one into the clock of the next): f(out) = f(clock) / 2^n 1 kHz clock: 500 Hz, 250 Hz, 125 Hz, 62.5 Hz after stages 1, 2, 3, 4. The 555 + 74HC74 build in section 12 divides a 1 Hz blinker by two.

8. Counters and shift registers: more outputs and inputs from few pins

The counter: 74HC161

A counter is a row of flip-flops that counts clock pulses in binary. The 74HC161 is a 4-bit synchronous counter (all four flip-flops share the clock, so the outputs change together and do not glitch through wrong codes); the cheaper ripple counters like the 74HC4040 clock each stage from the previous one, so the outputs briefly show wrong codes while the edge ripples through (about 10 to 15 ns per stage).

74HC161, DIP-16, notch at the left: pin 16 VCC 15 TC 14 Q0 13 Q1 12 Q2 11 Q3 10 CET 9 PE-bar (top row) pin 1 MR-bar 2 CP 3 D0 4 D1 5 D2 6 D3 7 CEP 8 GND (bottom row) CP = clock (rising edge) MR-bar = asynchronous clear (LOW clears to 0000) PE-bar = parallel enable (LOW loads D0 to D3 on the next clock) CEP, CET = count enables: both HIGH to count. TC = terminal count: HIGH when the count is 15 (and CET is HIGH). Q0 is the least significant bit. Count sequence: 0000, 0001, 0010 ... 1111, then 0000. f(Q0) = f/2, f(Q1) = f/4, f(Q2) = f/8, f(Q3) = f/16 Wire for plain counting: MR-bar, PE-bar, CEP, CET to VCC. Cascading to 8 bits: TC of the first chip goes to CET of the second (and the clocks join). Robot use: a wheel encoder gives 20 kHz pulses at full speed, too fast to count in software on a slow processor. Count them in hardware or divide by 16: 20 kHz / 16 = 1.25 kHz at Q3, which the program handles easily. To count to N other than 16, decode N and clear: a decade counter (0 to 9) is made with MR-bar = NAND(Q3, Q1), because 10 = 1010 is the first count with both Q3 and Q1 HIGH. The clear is asynchronous, so the count of 10 appears for a few nanoseconds: a glitch. Cleaner: detect 9 (1001) with PE-bar = NAND(Q3, Q0) and D0 to D3 tied LOW, so the next clock loads 0000 instead of 1010 (a synchronous load, no glitch); or use a counter built for it (74HC160).

The shift register: more outputs (74HC595)

A microcontroller never has quite enough pins. A serial-in, parallel-out shift register turns three output pins into eight (or sixteen, or sixty-four, by chaining): bits are pushed in one at a time on a data line, and then all eight leave together on the outputs.

74HC595, DIP-16, notch at the left: pin 16 VCC 15 Q0 14 DS 13 OE-bar 12 STCP 11 SHCP 10 SRCLR-bar 9 Q7' (serial out) (top row) pin 1 Q1 2 Q2 3 Q3 4 Q4 5 Q5 6 Q6 7 Q7 8 GND (bottom row) DS (data in) SHCP (shift clock: data shifts one place on each rising edge) STCP (storage clock: copies the shift register to the outputs on a rising edge) OE-bar LOW enables the outputs; SRCLR-bar HIGH = normal (LOW clears the shift register); Q7' = the bit that falls out of the end: join it to the next chip's DS. To send one byte (8 bits, most significant first): for each bit: put the bit on DS, then pulse SHCP. After 8 bits, pulse STCP once: all 8 outputs change together. Control pins used: DS, SHCP, STCP = 3 (plus 3.3 V or 5 V, ground). Chain a second chip: Q7' -> DS of the 2nd, SHCP and STCP shared: 16 outputs from the same 3 pins. Time to update 16 outputs at a 1 MHz clock: 16 bits x 1 us = 16 us. In Arduino: shiftOut() or the SPI library (clock = SHCP, data = DS, chip select = STCP). Limits: each output about 6 mA for guaranteed levels, and about 70 mA total through the VCC and GND pins. 8 red LEDs at 6 mA = 48 mA: fine. 8 LEDs at 10 mA = 80 mA: over the limit. Never drive a motor from an output: use the transistor stage of Basic Electronics 6.

The shift register in reverse: more inputs (74HC165)

74HC165, DIP-16 (parallel-in, serial-out), notch at the left: pin 16 VCC 15 CE-bar 14 D3 13 D2 12 D1 11 D0 10 DS (serial in) 9 Q7 (top row) pin 1 PL-bar 2 CP 3 D4 4 D5 5 D6 6 D7 7 Q7-bar 8 GND (bottom row) D0 to D7: eight parallel inputs (bumper switches, each with its pull-up). PL-bar LOW loads all eight into the register at once ("snapshot"). CP: clock; after the snapshot each rising edge moves the next bit to Q7 (pin 9); CE-bar LOW enables the clock (tie LOW); DS: serial in, to chain a second chip. Reading 8 inputs: pulse PL-bar low then high, then for each bit: read Q7, pulse CP. Three pins (PL-bar, CP, Q7) read all eight. Chain two chips (Q7 of the first into DS of the second, CP and PL-bar shared): 16 inputs for the same 3 pins; the read takes 16 us at 1 MHz. Unused D inputs: tie to VCC or GND. A 74HC165 input is a normal CMOS input: floating inputs give random readings.

9. The 555 timer

The 555 (1971 and still made) is the best-selling timing chip: two comparators, a flip-flop and a transistor in one 8-pin package, with a few resistors and a capacitor outside it. It makes a steady stream of pulses (the astable mode: a blinker, a clock, a PWM source) or one pulse of a set length when triggered (the monostable mode: a delay or a pulse stretcher). The ideas are all in this book already: a comparator (Basic Electronics 7), an RC charge curve (Basic Electronics 4) and an SR flip-flop (section 7).

Inside the 555 (the name comes from the three 5 k resistors): Vcc (8) o----+------------------------------+ | | [ 5 k ] (supply to all) +---------- 2/3 Vcc ------ also on pin 5 (CONTROL) [ 5 k ] +---------- 1/3 Vcc [ 5 k ] | GND (1) o----+ THRESHOLD (6) ------->(+)[ comparator 1 ](-)<-- 2/3 Vcc ----+ +--> RESET input of the SR flip-flop ---+---> output stage ---> OUT (3) TRIGGER (2) ------->(-)[ comparator 2 ](+)<-- 1/3 Vcc ----+--> SET input of the SR flip-flop | discharge transistor ---> DISCHARGE (7) RESET-bar (4): LOW forces OUT low (tie HIGH to disable) TRIGGER below 1/3 Vcc => flip-flop SET: OUT goes HIGH, discharge transistor OFF THRESHOLD above 2/3 Vcc => flip-flop RESET: OUT goes LOW, discharge transistor ON (pulls pin 7 to ground) Pins (DIP-8, notch at the left, pin 1 at the bottom-left): pin 8 VCC pin 7 DISCHARGE pin 6 THRESHOLD pin 5 CONTROL pin 1 GND pin 2 TRIGGER pin 3 OUT pin 4 RESET-bar

Astable operation

+Vcc o----+---------------------+------ pin 8 (VCC) and pin 4 (RESET-bar) | | [ R1 ] | pin 5 (CONTROL): 10 nF to GND (always, with a bipolar NE555) | | +----- pin 7 (DISCH) | pin 3 = the output | | [ R2 ] | | | +----- pin 6 (THRESH) | +----- pin 2 (TRIG) | | [ C ] | 0 V o------+----- pin 1 (GND) Capacitor C charges through R1 + R2 and discharges through R2 (pin 7 pulls to ground). Its voltage swings between 1/3 Vcc and 2/3 Vcc. charging (OUT HIGH): from Vcc/3 toward Vcc, stopping at 2Vcc/3: t_high = (R1 + R2) C ln( (Vcc - Vcc/3) / (Vcc - 2Vcc/3) ) = 0.693 (R1 + R2) C discharging (OUT LOW): from 2Vcc/3 toward 0, stopping at Vcc/3: t_low = R2 C ln( (2Vcc/3) / (Vcc/3) ) = 0.693 R2 C (ln 2 = 0.693; Vcc cancels: the frequency does not depend on the supply voltage.) period T = 0.693 (R1 + 2 R2) C f = 1 / T = 1.44 / ( (R1 + 2 R2) C ) duty = t_high / T = (R1 + R2) / (R1 + 2 R2) Worked example, a blinker (R1 = 1 k, R2 = 68 k, C = 10 uF): t_high = 0.693 x 69 k x 10 uF = 0.478 s t_low = 0.693 x 68 k x 10 uF = 0.471 s T = 0.949 s f = 1.053 Hz (1.44 gives 1.051 Hz) duty = 69 k / 137 k = 50.4 %. With R1 much smaller than R2 the duty is very close to 50 %, but it can never be below 50 %. Worked example, 1 kHz at 60 % duty (C = 10 nF): duty 0.6 requires R2 = 2 R1; f = 1.44 / (5 R1 C) gives R1 = 28.8 k Choose E12 R1 = 27 k, R2 = 56 k: f = 1.44 / (139 k x 10 nF) = 1036 Hz; duty = 83 k / 139 k = 59.7 % To get a duty below 50 %, put a diode (1N4148) across R2, anode on the pin 7 side: the charging current then bypasses R2 (t_high is about 0.693 R1 C, a little more because of the diode's 0.5 V drop) while the discharge still goes through R2. Build 3 uses two diodes to steer both paths. Tolerances: an electrolytic capacitor is +/-20 % and the 555 itself adds a percent or so, so a 1 Hz blinker really runs at 0.85 to 1.3 Hz; use a film or C0G capacitor for accurate timing.

Monostable operation

+Vcc o----+---------------------+------ pin 8 and pin 4 | | [ R ] | pin 5: 10 nF to GND | | +----- pin 7 (DISCH) | trigger: pin 2 held HIGH by a pull-up (10 k to Vcc); a brief pulse to 0 V starts the output pulse +----- pin 6 (THRESH) | [ C ] | 0 V o------+----- pin 1 At rest the discharge transistor holds C empty and OUT is LOW. A falling edge on pin 2 (below Vcc/3) sets the flip-flop: OUT HIGH, the transistor releases C, and C charges through R toward Vcc until it reaches 2Vcc/3, when the flip-flop resets, OUT goes LOW and C is emptied again. t = R C ln( (Vcc - 0) / (Vcc - 2Vcc/3) ) = R C ln 3 = 1.0986 R C about t = 1.1 R C R = 100 k, C = 10 uF: t = 1.1 x 100 k x 10 uF = 1.1 s For a 2 s pulse choose R = 180 k, C = 10 uF: t = 1.98 s (with a -20 % / +20 % capacitor 1.58 to 2.38 s) The trigger pulse must be shorter than t (a longer one just holds OUT HIGH); a re-trigger during the pulse is ignored. Robot use: turn the beeper on for exactly 0.5 s after a bump, hold a motor on for a fixed time, stretch a 1 ms sensor pulse so that a slow program does not miss it.

Which 555?

Bipolar NE555 / LM555CMOS TLC555 / LMC555 / ICM7555
Supply4.5 to 16 Vabout 2 to 15 V
Supply current3 to 10 mAabout 0.1 to 0.2 mA
OUT HIGH at 5 Vabout 3.3 V (VCC minus 1.7 V): below the 3.5 V that a 74HC input needs at 5 V!almost the full supply (4.5 to 5 V)
Output drive200 mA: can drive a small load directly; spikes in the supply when switching (needs a 10 µF + 100 nF)tens of mA at most; smoother supply
Top frequencyabout 100 to 500 kHzabout 1 to 2 MHz
ChooseDriving a heavy load directly (a relay, a buzzer), 9 V or 12 V supply3.3 V and 5 V logic, battery power, clocking a 74HC chip

The builds use a TLC555 (the same pins as the NE555).

10. Level shifting between 3.3 V and 5 V

The parts of a robot do not all use the same voltage: an Arduino Uno or Nano is 5 V, but a Raspberry Pi Pico, an ESP32 and a Raspberry Pi are 3.3 V; many sensors, motor drivers and LED strips are 5 V. Joining a 3.3 V pin to a 5 V pin needs thought in both directions:

DirectionThe problemFixes
5 V output to a 3.3 V inputOver-voltage: 5 V exceeds the 3.3 V + 0.3 V absolute maximum of most 3.3 V chips; the protection diodes conduct and the pin or the chip diesResistor divider (slow signals); 74LVC buffer powered at 3.3 V (its inputs tolerate 5.5 V); a level-shifter module; a MOSFET shifter; open-drain with a 3.3 V pull-up
3.3 V output to a 5 V inputUnder-voltage: 3.3 V (2.6 V worst case) falls below the 5 V CMOS VIH = 0.7 VCC = 3.5 V; sometimes works, sometimes fails with the temperature, noise or the batch of chips74HCT or 74AHCT buffer powered at 5 V (input threshold 2.0 V); a level-shifter module; a MOSFET shifter; a transistor

Down-shifting: a resistor divider

5 V signal o----[ R1 1 k ]----+----o to the 3.3 V input | [ R2 2 k ] | 0 V o-----------------------+ Vout = 5 V x R2 / (R1 + R2) = 5 x 2 / 3 = 3.33 V (a LOW stays 0 V) Speed: the divider's resistance seen by the pin is R1 || R2 = 667 ohm; with 15 pF of pin and wire capacitance: rise time (10 % to 90 %) = 2.2 x 667 x 15 pF = 22 ns so the signal can be up to a few MHz. Wire capacitance of 100 pF would give 147 ns. Disadvantages: it only works in one direction (5 V to 3.3 V), and loads the 5 V output with 5 V / 3 k = 1.7 mA. Good for a single signal, such as a UART line.

Up-shifting and the one-chip approach

For a 3.3 V board driving a 5 V device (a motor driver, an LED strip), use a 74HCT or 74AHCT buffer powered at 5 V: its input threshold is 2.0 V, so 3.3 V is a clean HIGH, and its output is a full 5 V. The 74AHCT125 (four buffers, with output-enable pins) is the usual chip; a 74HCT04 works too. Remember the NMH of 0.64 V: keep the wire short. For the other direction in a single chip, a 74LVC245 (eight-bit) or 74LVC125 powered at 3.3 V reads 5 V inputs safely and outputs 3.3 V. Ready-made modules with eight channels use these chips.

Both directions at once: the MOSFET shifter

An I2C bus is open-drain and works in both directions on the same wire, so it needs a bidirectional shifter. One N-channel MOSFET (BSS138 or 2N7000) per line does it:

3.3 V (LV) 5 V (HV) | | [ 10 k ] [ 10 k ] | | LV line o-+---------------------[ S D ]--------------------+--o HV line [ BSS138 ] [ G ] | to the 3.3 V supply (LV) N-channel MOSFET: source to the LV line, drain to the HV line, gate to 3.3 V (LV). Its body diode points from the source to the drain. 1. Nobody pulls low: the LV line is at 3.3 V (pull-up), so VGS = 3.3 - 3.3 = 0: the MOSFET is OFF. The HV line is at 5 V through its own pull-up. 2. The 3.3 V side pulls its line to 0 V: the source drops to 0, VGS = 3.3 V (well above the threshold of about 1.3 V): the MOSFET turns ON and pulls the HV line to 0 V. 3. The 5 V side pulls its line to 0 V: the drain is 0 V, the body diode conducts and pulls the source (LV line) to about 0.6 V; then VGS = 3.3 - 0.6 = 2.7 V, the MOSFET turns ON and takes the LV line all the way to 0 V. Both directions work with no direction pin. Ready-made 4 and 8 channel modules for 3.3 V / 5 V I2C use exactly this circuit; use a 4.7 k or 10 k pull-up on each side (the pull-up formula of section 5 applies to each side).
Never assume 5 V tolerance
The pins of a Raspberry Pi, a Pico and an ESP32 are not 5 V tolerant (about 3.6 V is the absolute maximum). A 5 V signal that appears to work may be slowly damaging the input. When in doubt, measure the signal with a meter before connecting it, and check the datasheet's absolute-maximum table. The reverse is easier: a 5 V Arduino input usually reads 3.3 V as HIGH, since the ATmega328P's threshold is 3.0 V at 5 V, but with only 0.3 V of margin.

11. Which board for logic work?

JobBest boardWhy
A first robot, 74HC chips, bumper switches and LED outputs, simple codeArduino Uno or Nano5 V logic matches 74HC (and 74HCT) at 5 V with no shifting; rugged pins; shiftOut() and the SPI library drive a 74HC595 in two lines; tens of tutorials
The same chips on a 3.3 V robotRaspberry Pi PicoRun the 74HC chips from 3.3 V (they work from 2 V to 6 V) so no shifter is needed; the programmable I/O blocks (PIO) can shift data into a 595 or from a 165, count pulses and make exact LED-strip timing in hardware
Counting fast encoder pulsesRaspberry Pi Pico (PIO) or ESP32 (pulse-counter peripheral)Hardware counting avoids missed pulses when the program is busy; otherwise a 74HC161 divide-by-16 in front of any board
Logic plus Wi-Fi, sensors on a busESP323.3 V, many pins, a hardware pulse counter; the 0.17 V NMH in section 1 is a reason to buffer 5 V devices with a 74HCT or 74AHCT chip
A full Raspberry Pi running LinuxRaspberry Pi with an external 595 / 165Its pins are 3.3 V only and cannot make precise timing in software; offload to a 74HC595 on hardware SPI and level-shift anything that is 5 V
Timing or blinking with no processor at allNone: a 555 and a 74HC74Cheap, instant on, no code to hang: a safe place for the watchdog or a fault-lamp of a robot

Basic Electronics 10 uses these chips from code and Basic Electronics 11 compares the boards in full.

12. Build it: a transistor NAND, a 555 blinker with a flip-flop, and a PWM motor-speed controller

Three small builds. Build 1 is a NAND gate made from two transistors, measured against a real 74HC00. Build 2 is a 555 blinker clocking a 74HC74 as a divide-by-two. Build 3 is the 555 as a pulse-width-modulation (PWM) speed control for a small DC motor, switched by the logic-level MOSFET of Basic Electronics 6.

Power and static
Builds 1 and 2 run from 5 V (a breadboard power module set to 5 V, a USB supply, or the 5 V pin of an Arduino); measure it with the meter before you connect the chips. A 74HC chip is damaged above 7 V and a TLC555 above 18 V. Put a 100 nF capacitor across the supply rails next to each chip, tie every unused input (Build 2 shows how), and connect the power last. Touch a grounded metal object before handling the CMOS chips. Build 3 uses a separate battery pack for the motor, joined only at the ground rail.

Parts list

PartValueUsed in
Q1, Q22N3904 NPN transistor (TO-92)1
U374HC00 quad NAND, DIP-141 (comparison)
U1TLC555 (or LMC555) CMOS timer, DIP-82, 3
U274HC74 dual D flip-flop, DIP-142
Q3IRLZ44N logic-level N-channel MOSFET (TO-220; pins gate, drain, source from the left, label facing you)3
Rc1 kΩ (brown-black-red)1; R1 in builds 2 and 3
Ra, Rb (base resistors)10 kΩ (brown-black-orange), two1
R2 (build 2)68 kΩ (blue-grey-orange)2
R3 (LED1), R4 (LED2)2.2 kΩ (red-red-red) and 1 kΩ (brown-black-red)2
C (build 2)10 µF electrolytic, 16 V (+ leg to the timing node)2
C310 nF ceramic (pin 5 bypass), two2, 3
C1, C4100 nF ceramic, decoupling (one per chip)2
LED1, LED2Red, 5 mm, two2, 3
P1100 kΩ linear potentiometer3
R1 (build 3), Rd1 kΩ, two3
C (build 3)4.7 nF ceramic or film3
Rg, Rpd100 Ω (brown-black-brown) and 100 kΩ3
D1, D21N4148 signal diode, two3
D31N4001 (flyback diode)3
MotorSmall 3 to 6 V hobby DC motor (about 150 mA running, 600 mA stalled) and a 4 × AA battery holder (6 V)3
Supply5 V (module, USB or board)all
Breadboard, jumpers, multimeterA meter with a duty-cycle or frequency range is useful but not requiredall

Build 1: a NAND gate from two transistors

Two NPN transistors in series with a collector resistor, as in section 3. The inputs are two jumper wires that you plug into the + rail (1) or the − rail (0).

+5 V o------+ | [ Rc 1 k ] | +----------------o OUT (the gate output: measure it here) | C A o-[ Ra 10 k ]-B Q1 (2N3904) E | C B o-[ Rb 10 k ]-B Q2 (2N3904) E | 0 V o-------+ Check the transistors will saturate (both inputs HIGH = 5 V): Base current Ib = (5 V - 0.7 V) / 10 k = 0.43 mA Collector current Ic = (5 V - 0.2 V) / 1 k = 4.8 mA Forced gain = Ic / Ib = 4.8 / 0.43 = 11, far below the real gain (100 or more), so both transistors are driven hard into saturation. Each VCE(sat) about 0.1 V, so OUT = 0.1 V + 0.1 V = 0.2 V Q1's base sits at (0.1 V + 0.7 V) = 0.8 V above ground (it rides on Q2's VCE). If either input is LOW (0 V) its transistor is OFF, no current can flow through the series pair, and OUT is pulled up to 5 V. That is NAND. Power wasted when OUT is LOW: 5 V x 4.8 mA = 24 mW, constantly (the weakness of section 3).
Breadboard layout. Top rails: + rail = 5 V, - rail = 0 V. Columns have rows a-e joined and rows f-j joined. TO-92 transistors: flat face towards you, legs down, left to right = emitter, base, collector (the usual 2N3904 order; check your datasheet). Transistors in row c: Q1: emitter column 10 row c, base column 11 row c, collector column 12 row c Q2: emitter column 16 row c, base column 17 row c, collector column 18 row c Series connection: jumper column 10 row a -> column 18 row a (Q1 emitter to Q2 collector) Ground: jumper column 16 row a -> top - rail (Q2 emitter) Collector resistor: Rc (1 k): column 12 row a -> column 15 row a; jumper column 15 row b -> top + rail Base resistors: Ra (10 k): column 11 row b -> column 5 row b; input A = the free jumper in column 5 row d Rb (10 k): column 17 row b -> column 22 row b; input B = the free jumper in column 22 row d (plug the other end of each input jumper into the + rail for 1 or the - rail for 0) Measure: OUT = red probe column 12 row e, black on the - rail; Q1 base = column 11 row e; Q2 base = column 17 row e Connect the power LAST. Compare with a real gate (74HC00, DIP-14 in row e columns 30 to 36, row f 36 to 30, notch at the left; pins as in section 4): power: pin 14 -> + rail, pin 7 -> - rail, 100 nF across the rails next to it; gate 1: A = pin 1, B = pin 2, output = pin 3. Tie the unused gates' inputs (pins 4, 5, 9, 10, 12, 13) to the - rail. Wire pin 3 to a 1 k + LED to ground to see the output: LED current = (about 4.9 V - 2.0 V) / 1 k = 2.9 mA.
  1. Set A = 0, B = 0 (both jumpers on the − rail): OUT reads 5.0 V. Then A = 0, B = 1 and A = 1, B = 0: OUT still 5.0 V.
  2. Set A = 1, B = 1: OUT drops to about 0.2 V; the voltage across Rc is about 4.8 V (4.8 mA); Q1's base reads about 0.8 V and Q2's about 0.7 V.
  3. Leave input A unconnected (floating) with B = 1: OUT wanders: a floating input is neither HIGH nor LOW. Touch the loose wire with a finger and watch OUT follow your hum.
  4. Wire the 74HC00 as above and repeat the four combinations. OUT is 5 V or 0 V (the 74HC output goes almost to the rails; the transistor version can only reach 0.2 V).
  5. Threshold test: hold B = 1, connect input A of the 74HC00 to the wiper of a 10 kΩ pot across the supply and turn it while watching the LED. The output flips at about 2.5 V (half the supply). Do the same with the transistor gate: it flips at about 0.65 V (one base-emitter drop): a much worse noise margin.

Build 2: a 555 blinker clocking a flip-flop

The TLC555 oscillates at about 1 Hz; its output drives LED1 and also the clock of one 74HC74 flip-flop wired as a toggle, whose Q output drives LED2 at half the rate.

+5 V o------+---------------+---- U1 pin 8, pin 4; U2 pin 14, pin 1 (1RD-bar), pin 4 (1SD-bar); U2 pins 10, 13 | [ R1 1 k ] U1 = TLC555: pin 1 GND, pin 2 TRIG, pin 3 OUT, pin 4 RESET-bar, | pin 5 CTRL (10 nF to GND), pin 6 THRESH, pin 7 DISCH, pin 8 VCC +--------- pin 7 | [ R2 68 k ] | +--------- pin 6 and pin 2 (joined) | [ C 10 uF ] (+ at the top) | 0 V o-------+ U1 pin 3 (OUT) ----+---- [ R3 2.2 k ] ---- LED1 ---- 0 V t_high = 0.478 s, t_low = 0.471 s, f = 1.05 Hz | +---- U2 pin 3 (1CP, the clock) U2 = 74HC74, flip-flop 1: pin 2 (1D) wired to pin 6 (1Q-bar) (toggle: D = the opposite of Q) pin 5 (1Q) ---- [ R4 1 k ] ---- LED2 ---- 0 V pins 1 and 4 (RD-bar, SD-bar): to +5 V (inactive) Unused flip-flop 2: pin 13 (2RD-bar) and pin 10 (2SD-bar) to +5 V; pin 12 (2D) and pin 11 (2CP) to 0 V; pins 8, 9 left open (no floating inputs) Decoupling: 100 nF across the supply at U1 and at U2 Frequency check: T = 0.693 x (R1 + 2 R2) x C = 0.693 x 137 k x 10 uF = 0.949 s f(LED1) = 1.053 Hz f(LED2) = 0.527 Hz, duty exactly 50 %
Breadboard layout. Top rails: + rail = 5 V, - rail = 0 V. C1 (100 nF) across the top rails next to U1, C4 (100 nF) across the rails next to U2. U1 (TLC555) straddles the centre gap, notch towards column 1: pins 1 to 4 in row e, columns 10 to 13; pins 8 to 5 in row f directly opposite. U1 pin 1 = column 10 row e pin 2 = column 11 row e pin 3 = column 12 row e pin 4 = column 13 row e U1 pin 8 = column 10 row f pin 7 = column 11 row f pin 6 = column 12 row f pin 5 = column 13 row f Power: jumper column 10 row g -> top + rail (pin 8, VCC) jumper column 10 row a -> top - rail (pin 1, GND) jumper column 13 row a -> top + rail (pin 4, RESET-bar held HIGH) Control: C3 (10 nF): column 13 row g -> column 15 row g; jumper column 15 row h -> top - rail (pin 5 to ground) Join 2 and 6: jumper column 11 row b -> column 12 row h (pin 2 to pin 6: the timing node) R1 (1 k): column 11 row g -> column 17 row g; jumper column 17 row h -> top + rail (VCC to pin 7) R2 (68 k): column 11 row i -> column 18 row i; jumper column 18 row j -> column 12 row i (pin 7 to pin 6) C (10 uF): + leg column 11 row d, - leg column 14 row d; jumper column 14 row b -> top - rail (timing node to ground; + leg on the node) LED1: R3 (2.2 k): column 12 row b -> column 22 row b; LED1 anode column 22 row c, cathode column 23 row c; jumper column 23 row d -> top - rail U2 (74HC74): pins 1 to 7 in row e columns 30 to 36, pins 14 to 8 in row f directly opposite (pin 14 across from pin 1 in column 30), notch at the left. pin 1 = column 30 e pin 2 = column 31 e pin 3 = column 32 e pin 4 = column 33 e pin 5 = column 34 e pin 6 = column 35 e pin 7 = column 36 e pin 14 = column 30 f pin 13 = column 31 f pin 12 = column 32 f pin 11 = column 33 f pin 10 = column 34 f pin 9 = column 35 f pin 8 = column 36 f Power: jumper column 30 row g -> top + rail (pin 14); jumper column 36 row a -> top - rail (pin 7) Inactive set/reset of flip-flop 1: jumper column 30 row a -> top + rail (pin 1); jumper column 33 row a -> top + rail (pin 4) Toggle: jumper column 31 row b -> column 35 row b (pin 2, 1D, to pin 6, 1Q-bar) Clock: jumper column 12 row c -> column 32 row c (U1 pin 3 to U2 pin 3, 1CP) LED2: R4 (1 k): column 34 row d -> column 38 row d; LED2 anode column 38 row b, cathode column 39 row b; jumper column 39 row c -> top - rail Unused flip-flop 2: jumper column 31 row g -> top + rail (pin 13); jumper column 34 row g -> top + rail (pin 10); jumper column 32 row g -> top - rail (pin 12); jumper column 33 row g -> top - rail (pin 11) Connect the power LAST. Measure: OUT = red probe column 12 row a; timing node = column 11 row c; Q = column 34 row a; (black probe on the - rail for all) (if your board has bottom power rails, use them for the lower-half jumpers and link them to the top rails)
  1. Power on. LED1 flashes about once a second, about equally on and off. LED2 flashes at half the rate, and changes state only at the moment LED1 turns on (the rising edge).
  2. Count 20 flashes of LED1 with a stopwatch: about 19 s for the calculated 0.949 s each (anywhere from 15 to 25 s is normal with a 20 % capacitor).
  3. Meter on the timing node (pin 2/6): about 2.5 V steady on a digital meter, the average of a signal swinging between 1.67 V and 3.33 V. Meter on OUT: about 2.5 V average (a rapidly switching signal reads its average).
  4. Change C to 1 µF: the blinker runs ten times faster (10.5 Hz, too fast to count but a visible flicker); LED2 at 5.3 Hz.
  5. Disconnect pin 2 (1D) from pin 6 and tie it to the + rail: LED2 stays on after the first clock edge, because D is always 1: a flip-flop remembers D at the clock edge.
  6. Try the unused-input rule: disconnect pin 12 (2D) and pin 11 (2CP) from the rail. The second flip-flop is not connected to anything, but the supply current of the chip can rise and the chip warm slightly; floating inputs do harm even with no visible effect.

Build 3: PWM motor-speed control with the 555

Pulse-width modulation switches a motor fully on and fully off, thousands of times a second; the fraction of the time that it is on (the duty cycle D) sets the average voltage, and so the speed. The 555's duty cannot go below 50 % with the plain circuit, so two diodes steer the capacitor's charge and discharge currents through different parts of the potentiometer: moving the wiper trades charge time against discharge time while the total stays almost constant, so the frequency stays near-constant and only the duty changes.

+5 V o-----+-----------------------------------------------+---- U1 pin 8 and pin 4 (reset) | [ R1 1 k ] | +--------------------- U1 pin 7 (DISCH): call this node M | D1 | anode at M, cathode towards the pot's end A D2: anode on the Rd side, cathode at M | | +--------[ A P1 100 k B ]--------[ Rd 1 k ]--------+---- joins M again | W (wiper) +------------------ U1 pin 6 and pin 2 (joined): the timing node K | [ C 4.7 nF ] | 0 V o------------------------+ Charging path (OUT HIGH): +5 V -> R1 -> D1 -> A end of P1 -> wiper -> K (capacitor). D2 is reverse biased: no current. Discharge path (OUT LOW): K -> wiper -> B end of P1 -> Rd -> D2 -> M -> pin 7 (pulled to ground by the chip). D1 is reverse biased (M = 0 V). With the wiper a fraction p of the way from A to B (R_AW = p x 100 k): charge resistance Ra = 1 k + p x 100 k discharge resistance Rb = 1 k + (1 - p) x 100 k Ra + Rb = 102 k at every position Ideal (no diodes): t_high = 0.693 Ra C, t_low = 0.693 Rb C, T = 0.693 x 102 k x 4.7 nF = 0.332 ms, f = 3.01 kHz, duty D = Ra / (Ra + Rb) = (1 + 100 p) / 102 The diodes' 0.5 V drop changes the maths: the capacitor charges toward Vcc - 0.5 V and discharges toward -0.5 V, not 0 V: t_high = 0.887 Ra C t_low = 0.571 Rb C (from ln((5-0.5-1.667)/(5-0.5-3.333)) = 0.887 and ln((3.333+0.5)/(1.667+0.5)) = 0.571) so the real duty is somewhat above the ideal: D = 0.887 Ra / (0.887 Ra + 0.571 Rb), and the frequency a little lower. p Ra Rb ideal D ideal f real D (diode-corrected) real f 0.25 26 k 76 k 25.5 % 3.01 kHz about 35 % about 3.2 kHz 0.50 51 k 51 k 50.0 % 3.01 kHz about 61 % about 2.9 kHz 0.75 76 k 26 k 74.5 % 3.01 kHz about 82 % about 2.6 kHz Duty goes from about 1 % to about 99 % over the pot's travel. The exact value depends on the diodes (a 1N4148 drops 0.4 to 0.6 V depending on the current), so treat the real column as +/- 5 points. A 3 kHz PWM frequency is a little audible (a faint whine); a smaller C (2.2 nF, about 6 kHz) quietens it. Output stage (Basic Electronics 6): OUT (pin 3) -> Rg 100 ohm -> MOSFET gate; Rpd 100 k from gate to 0 V (the motor stays off if the 555 is not driving); MOSFET source to 0 V, drain to the motor's lower terminal; motor's upper terminal to the battery pack +6 V; D3 (1N4001) across the motor, cathode to +6 V (flyback). Pack - to the circuit's 0 V (one common ground). Average motor voltage = D x 6 V (ignoring the MOSFET's 0.02 ohm). Gate drive: the average gate current is Qg x f = 48 nC x 3 kHz = 0.14 mA (Qg = 48 nC maximum for the IRLZ44N), so the 555 can drive it with no extra driver.
Breadboard layout (clear the board first). Top rails: + rail = 5 V, - rail = 0 V. The motor battery pack connects only at column 46 row b (+) and the - rail (-). U1 (TLC555): same positions as Build 2: pin 1 = column 10 e, pin 2 = column 11 e, pin 3 = column 12 e, pin 4 = column 13 e; pin 8 = column 10 f, pin 7 = column 11 f, pin 6 = column 12 f, pin 5 = column 13 f. Power: jumper column 10 row g -> top + rail; jumper column 10 row a -> top - rail; jumper column 13 row a -> top + rail (pin 4) Control: C3 (10 nF): column 13 row g -> column 15 row g; jumper column 15 row h -> top - rail Timing node K (pins 2 and 6): jumper column 11 row b -> column 12 row h Capacitor: C (4.7 nF): column 11 row c -> column 14 row c; jumper column 14 row a -> top - rail Node M (pin 7, column 11 rows f to j): R1 (1 k): column 11 row g -> column 17 row g; jumper column 17 row h -> top + rail D1: anode column 11 row h, cathode (banded end) column 16 row h; jumper column 16 row i -> column 24 row i D2: anode column 30 row h, cathode (banded end) column 34 row h; jumper column 34 row g -> column 11 row i Potentiometer P1: legs in row j: end A = column 24 row j, wiper = column 25 row j, end B = column 26 row j (A is the end joined to D1; B the end joined to Rd) wiper to K: jumper column 25 row i -> column 11 row d Rd (1 k): column 26 row i -> column 30 row i Output stage (MOSFET Q3 legs in row c: gate column 40, drain column 41, source column 42): Rg (100 ohm): column 12 row b -> column 16 row b; jumper column 16 row c -> column 40 row a (pin 3 to the gate) Rpd (100 k): column 40 row d -> column 44 row d; jumper column 44 row e -> top - rail Source: jumper column 42 row a -> top - rail Motor: one wire in column 41 row a (drain), the other in column 46 row a; jumper column 46 row b = battery pack + (red lead) D3 (1N4001): anode column 41 row e, cathode (banded end) column 46 row e Battery pack -: black lead to the top - rail. LED1 (brightness follows duty): R3 (2.2 k): column 12 row d -> column 22 row d; LED anode column 22 row c, cathode column 23 row c; jumper column 23 row b -> top - rail Connect the 5 V LAST, then the motor pack. Measure: pin 3 average voltage = red probe column 12 row a; drain voltage = red probe column 41 row d (the motor's voltage is 6 V minus this; its average is 6 V x (1 - D)); (black probe on the - rail for all)
  1. Turn P1 fully towards end A (p = 0): LED1 almost off, the motor is stopped. Pin 3 average about 0.05 to 0.1 V (D about 1 to 2 %).
  2. Turn it a quarter of the way (p = 0.25): LED1 dim; pin 3 reads about 1.7 V (D about 35 %); the motor is about to start (hobby motors need about 2 V average to overcome friction; the average at this position is 6 V × 35 % = 2.1 V).
  3. Half way (p = 0.5): pin 3 about 3.0 V (D about 61 %), the motor runs at medium speed; three quarters: about 4.0 V (D about 82 %); fully towards B: LED1 full and the motor at full speed (pin 3 about 4.9 V).
  4. Speed in relation to duty: motor speed is close to proportional to the average voltage D × 6 V above the stall point (the motor acts like a low-pass filter on the pulses: its winding inductance of a few mH and its inertia average the 3 kHz).
  5. Remove D3 for a moment (power off first): the drain terminal shows spikes above 6 V when the MOSFET switches off the inductive load (the flyback voltage of Basic Electronics 5). With D3 in place the drain never exceeds about 6.7 V.
  6. Compare the frequency at each position with a frequency meter or the simulator: it changes from about 3.2 kHz to 2.6 kHz as p goes from 0.25 to 0.75, not exactly constant, as the table predicts.

Simulators

Falstad Circuit Simulator (falstad.com/circuit): gates, flip-flops, counters and the 555 are in the Draw menu under the Logic Gates and Digital Chips groups (and the Circuits menu has ready-made 555 astable and flip-flop examples, a good place to start). For Build 1, draw two NPN transistors from Active Components, add logic-level inputs via Inputs and Sources (a logic input element) and use a 5 V source; Falstad's transistors are ideal enough to give the 0.2 V low and 5 V high of the calculation. For Build 2, drop a 555 chip with R1, R2 and C; a D flip-flop with Q-bar joined to D divides by two, and the scope shows both traces. For Build 3, model the motor as a 40 Ω resistor in series with a 5 mH inductor (6 V / 0.15 A = 40 Ω), put D3 across both, and use a logic-level N-channel MOSFET (a plain MOSFET with a 5 V gate is enough); put a slider on the potentiometer resistance and watch the duty cycle on the scope.

Tinkercad Circuits (tinkercad.com): the component list has a 555 timer, a 74HC595 shift register, LEDs, push buttons, a DC motor, a power supply, a multimeter and an oscilloscope, and an Arduino Uno. Tinkercad's list of logic ICs has changed over time, so search it for the 74-series chips (hex inverter, quad NAND and flip-flop); if one is missing, build the same function from the transistors or use Falstad for that chip. Its 555 follows the same formulas; set R1, R2 and C and measure the output with the oscilloscope, which gives the period and duty directly. A 74HC595 with an Arduino and the shiftOut() function is a good simulation of the three-pin expansion of section 8.

Expected readings

MeasurementCalculatedReal (typical)Simulator
1: transistor NAND, OUT for A,B = 00, 01, 105.0 V4.98 to 5.00 V (no load)5.0 V
1: OUT for A = B = 10.2 V0.10 to 0.30 V0.1 to 0.2 V
1: voltage across Rc when A = B = 14.8 V (4.8 mA)4.7 to 4.9 V4.8 V
1: Q1 base / Q2 base when A = B = 10.8 V / 0.7 V0.75 to 0.85 V / 0.65 to 0.75 V0.8 V / 0.7 V
1: 74HC00 OUT high / low5 V / 0 V4.9 V (with the 1 k + LED) / 0.00 V5 V / 0 V
1: 74HC00 switching thresholdabout 2.5 V2.2 to 2.8 V (guaranteed outside 1.5 to 3.5 V)about 2.5 V
1: transistor gate switching thresholdabout 0.65 V0.55 to 0.75 V0.65 V
2: 555 f / thigh / tlow1.053 Hz / 0.478 s / 0.471 s0.85 to 1.3 Hz (C is ±20 %)1.053 Hz (exact values entered)
2: duty of OUT50.4 %49 to 52 %50.4 %
2: timing node (pin 2/6) average / swing2.5 V / 1.67 to 3.33 V2.4 to 2.6 Vswing 1.67 to 3.33 V on the scope
2: OUT high / low5 V / 0 V4.5 to 5.0 V (with LED) / 0.05 to 0.15 V5 V / 0 V
2: LED1 current / LED2 current1.2 mA / 2.9 mA1.0 to 1.4 mA / 2.6 to 3.1 mA1.2 mA / 2.9 mA
2: LED2 (Q) f and duty0.527 Hz, 50 %half the LED1 rate; 50 % to within 1 %0.527 Hz
3: ideal frequency3.01 kHz2.6 to 3.3 kHz, falling as p rises3.01 kHz (ideal diodes)
3: duty at p = 0.25 / 0.5 / 0.7525.5 / 50.0 / 74.5 % (ideal); 35 / 61 / 82 % (with 0.5 V diode drops)35 / 61 / 82 % (± 5 points)ideal diodes give 25.5 / 50 / 74.5 %; add a 0.5 V drop to match
3: pin 3 average voltage at p = 0.25 / 0.5 / 0.751.7 / 3.0 / 4.0 V (real duty x 4.9 V)1.6 to 1.9 / 2.8 to 3.2 / 3.8 to 4.3 V(from the duty)
3: motor average voltage at the same positions2.1 / 3.7 / 4.9 V (6 V x real duty)within about 0.5 V (the flyback current adds a little)(from the duty)
3: gate average current0.14 mA (Qg f)not measured directly—

Real readings spread because the capacitor in Build 2 is a ±20 % part, diodes differ, the 555 has a timing error of a few percent and an LED's voltage varies between colours and batches. What does not vary is the structure: the transistor NAND is LOW only when both inputs are HIGH; the 74HC switches near half the supply and the transistor gate near 0.65 V; LED2 changes only on the rising edge of LED1 and runs at exactly half its rate; and in Build 3 the duty (and so the speed) rises as the wiper moves away from the D1 end while the frequency stays within about 20 % of 3 kHz.

13. Challenges

Challenge 1: Levels, margins and pull-ups
(a) Using the table in section 1, calculate NML and NMH for a 74HC output driving a 74HC input at 3.3 V, and for the same chip at 5 V driving a 74LS input. Then decide whether each of these connections works: an ESP32 pin driving a 74HC at 5 V; an ESP32 pin driving a 74HCT at 5 V (give the noise margins); a 74LS output driving a 74HC input at 5 V. (b) A 5 V Arduino output must feed a 3.3 V Pico input. Use R1 = 1 kΩ and choose R2 from the E12 series so that the output is as close as possible to 3.3 V without exceeding it; give the output voltage and the 10 % to 90 % rise time with 15 pF of load, and with a 100 pF wire instead. (c) Four open-drain sensors share one wire with a pull-up to 5 V. Each can sink 3 mA at 0.4 V. The wire capacitance is 200 pF and it must rise (30 % to 70 %) in 1 µs. Find the minimum and maximum pull-up, choose a standard value and give the rise time and the current when the wire is pulled low. A fifth, push-pull device is mistakenly added, with an output resistance of 65 Ω in each state: while it drives HIGH, a sensor holds the wire LOW with an on-resistance of about 130 Ω (0.4 V / 3 mA). Find the current and the voltage on the wire, and say whether that voltage is a valid LOW.
View solution
Challenge 2: Gates, latches and shift registers
(a) Build an XOR from four NAND gates and check all four input combinations of A and B by tracing each gate; state how many 74HC00 chips you need and what you must do with the unused pins. (b) For the NAND SR latch of section 7, trace the outputs Q and Q-bar through this input sequence (S-bar, R-bar): (1,1), (0,1), (1,1), (1,0), (1,1), (0,0), (1,1). Start with Q = 0. Mark the step that is forbidden and say what is wrong with the last step. (c) A robot needs 22 LED outputs and 12 bumper inputs from a board with only 6 spare pins. Choose the number of 74HC595 and 74HC165 chips, the pins used, the time to update all LEDs and to read all inputs at a 1 MHz clock, and check the 70 mA supply limit if every LED needs 6 mA (and say how many LEDs may be on at once if each needs 10 mA).
View solution
Challenge 3: The 555 and PWM
(a) Design a 555 astable at 1 kHz with about 60 % duty using C = 10 nF and E12 resistors: find R1 and R2 (use R2 = 2 R1 as a start), and the frequency and duty you actually get. Then find the frequency and times if the capacitor is 20 % too large. (b) Design a monostable that holds a beeper on for 2 s after a trigger, with C = 10 µF; find R from the E12 series and the pulse length, and the range for a ±20 % capacitor. (c) For Build 3 (R1 = Rd = 1 kΩ, P1 = 100 kΩ, C = 4.7 nF), find the ideal duty and frequency at p = 0.2, then the diode-corrected duty and frequency using kh = 0.887 and kl = 0.571, and the average motor voltage on a 6 V pack for each. A motor needs an average of 2.0 V to start: show that it will not turn at p = 0.2 but will at p = 0.3 (find the corrected duty and average voltage at p = 0.3 too), and say what the ideal formula would wrongly have predicted for p = 0.3.
View solution

Quick reference

  • Levels: output VOH must be at least the input's VIH, VOL at most VIL; NML = VIL − VOL, NMH = VOH − VIH, both must be positive. 74HC at 5 V: 1.5 / 3.5 V in, 0.1 / 4.4 V out; 74HCT in: 0.8 / 2.0 V
  • Gates: AND, OR, NOT, NAND, NOR, XOR; NAND alone makes all of them (NOT = NAND(A,A); OR = NAND of the inverted inputs); bubble or bar = active low or inverted
  • CMOS: complementary P and N MOSFETs, almost no current at rest; P = Cpd V2 f; propagation delay about 8 ns at 5 V, longer at 3.3 V
  • 74HC rules: tie every unused input to VCC or GND; 100 nF at every chip; never tie two push-pull outputs together; supply 2 to 6 V; fan-out is limited by speed, not DC current
  • Pull-ups: 10 kΩ typical for a button (0.5 mA pressed at 5 V); open-drain wired-AND: Rp between (VCC − VOL)/IOL and tr/(0.8473 C)
  • Schmitt trigger (74HC14): VT+ about 2.4 V, VT− about 1.4 V at 5 V; RC debounce delay = −RC ln(1 − VT+/VCC) = 0.65 RC
  • Memory: NAND SR latch (inputs active low, 00 forbidden); D flip-flop copies D on the rising clock edge (74HC74; set/reset tied high); Q-bar to D divides by 2
  • Counters and shift registers: 74HC161 counts to 15, f/2n on Qn; 74HC595 (DS, SHCP, STCP: 3 pins, 8 outputs, 6 mA each, 70 mA total); 74HC165 (PL-bar, CP, Q7: 3 pins, 8 inputs); chains multiply the outputs, not the pins
  • 555 astable: thigh = 0.693 (R1 + R2) C, tlow = 0.693 R2 C, f = 1.44 / ((R1 + 2R2) C), duty = (R1 + R2) / (R1 + 2R2); monostable: t = 1.1 R C; use a CMOS 555 for 3.3 V and 5 V logic
  • PWM: average voltage = D × Vsupply; steering diodes keep f nearly constant while D changes; MOSFET gate current average = Qg f
  • Level shifting: 5 V to 3.3 V: divider (R2/(R1+R2) = 2/3), 74LVC, or MOSFET; 3.3 V to 5 V: 74HCT or 74AHCT at 5 V; I2C: BSS138 shifter with a pull-up on each side; Pico, ESP32 and Raspberry Pi pins are not 5 V tolerant

Next, Basic Electronics 9 moves from signals to power: DC motors, servos and steppers at circuit level, H-bridge and motor-driver chips, relays, and the batteries, regulators and current budgets that keep a robot from browning out. The PWM idea of Build 3 returns there in a full H-bridge.