Basic Electronics, Chapter 8: Challenge 2 solution (gates, latches and shift registers)

Formulas: NAND(a, b) = NOT(a AND b)     XOR = N( N(A, M), N(B, M) ) with M = N(A, B)
          SR latch (inputs active low):  Q = NAND(S-bar, Q-bar)     Q-bar = NAND(R-bar, Q)
          serial transfer time = number of bits / clock frequency

(a) XOR from four NAND gates (N(x, y) = NAND of x and y)
      gate 1:  M = N(A, B)       gate 2:  P = N(A, M)       gate 3:  R = N(B, M)       gate 4:  Y = N(P, R)

        A  B |  M   P   R  | Y     expected A XOR B
        0  0 |  1   1   1  | 0     0
        0  1 |  1   1   0  | 1     1       (P = N(0,1) = 1;  R = N(1,1) = 0;  Y = N(1,0) = 1)
        1  0 |  1   0   1  | 1     1       (P = N(1,1) = 0;  R = N(0,1) = 1;  Y = N(0,1) = 1)
        1  1 |  0   1   1  | 0     0       (M = N(1,1) = 0;  P = N(1,0) = 1;  R = N(1,0) = 1;  Y = N(1,1) = 0)
      All four rows match.
    Chips needed: ONE 74HC00 (it holds exactly four NAND gates).
    Pin wiring:  gate 1: A -> pin 1, B -> pin 2, M = pin 3.      gate 2: A -> pin 4, M (pin 3) -> pin 5, P = pin 6.
                 gate 3: B -> pin 9, M (pin 3) -> pin 10, R = pin 8.      gate 4: pin 6 -> pin 12, pin 8 -> pin 13, Y = pin 11.
                 Power: pin 14 to VCC, pin 7 to GND, 100 nF across them.
    Unused pins: none. All four gates and all eight inputs are used, so there are no floating inputs to tie off.  (Pins 3, 6, 8 and 11 are outputs; leave pin 11 free
    for the load.)  Had you used only three gates, the fourth gate's two inputs would have to be tied to GND or VCC.

(b) NAND SR latch trace, starting with Q = 0 and Q-bar = 1
      step  (S-bar, R-bar)   Q   Q-bar   explanation
       1     (1, 1)          0    1      hold:  Q = N(1, 1) = 0;  Q-bar = N(1, 0) = 1
       2     (0, 1)          1    0      S-bar low: Q = N(0, ...) = 1;  then Q-bar = N(1, 1) = 0   -> SET
       3     (1, 1)          1    0      hold:  Q = N(1, 0) = 1;  Q-bar = N(1, 1) = 0
       4     (1, 0)          0    1      R-bar low: Q-bar = N(0, ...) = 1;  then Q = N(1, 1) = 0   -> RESET
       5     (1, 1)          0    1      hold
       6     (0, 0)          1    1      FORBIDDEN:  both gates have a low input, so both outputs are forced HIGH (Q and Q-bar are no longer opposites)
       7     (1, 1)          ?    ?      the last step: both inputs are released at once.  Each gate now sees (1, 1) and wants to go LOW, but each LOW would
                                        make the other gate go HIGH; the result depends on which gate is a few nanoseconds faster (a race), so the final state
                                        is unpredictable (it can also briefly oscillate or settle half-way: metastability).
      Lesson: never let both inputs go low together; with a changeover switch the second contact is open, so it cannot happen.

(c) 22 LED outputs and 12 bumper inputs with 6 spare pins
    Outputs: 22 / 8 = 2.75, so 3 x 74HC595 (24 outputs, 2 unused), chained: Q7' (pin 9) of each into DS of the next, SHCP and STCP shared.
        Pins used: DS, SHCP, STCP = 3 pins.
    Inputs: 12 / 8 = 1.5, so 2 x 74HC165 (16 inputs, 4 unused and tied to VCC or GND), chained through DS (pin 10), CP and PL-bar shared.
        Pins used: PL-bar, CP, Q7 = 3 pins.
    Total 3 + 3 = 6 pins: exactly the 6 spare pins.
    Times at a 1 MHz clock:
        update all LEDs: 24 bits x 1 us = 24 us  (plus the latch pulse STCP)
        read all inputs: 16 bits x 1 us = 16 us  (plus the load pulse PL-bar)
        both are far faster than a robot's control loop, which runs every few milliseconds.
    Current limit (about 70 mA through the VCC/GND pins of EACH chip; each 595 has its own supply pins):
        8 LEDs at 6 mA = 48 mA < 70 mA     OK, even with all of them on (22 LEDs all on = 22 x 6 = 132 mA is spread over three chips at 48 mA each)
        8 LEDs at 10 mA = 80 mA > 70 mA    not allowed.  At 10 mA each, at most 70 / 10 = 7 LEDs per chip may be on at once (or add transistors or a driver such as a ULN2803 / 74HC541)
    Also: each output is rated at about 6 mA for guaranteed levels, so 10 mA from one output is already beyond the spec.

Checklist
  - XOR = four NAND gates; every gate input is wired to something (no floating inputs).
  - Trace an SR latch one step at a time, using the "any low input forces HIGH" rule of NAND.
  - Chips x 8 = outputs/inputs; pins = 3 however many chips you chain; time = bits / clock; check the 70 mA per-chip limit.