Sequential Logic: Latches, Flip-Flops & Memory

Boolean Algebra & Digital Logic

Chapter 8 · Sequential Logic: Latches, Flip-Flops & Memory

Chapter 6 defined a combinational circuit as one whose output depends only on its current inputs, and named this chapter as the exception. The mechanism behind that exception is simple to state and genuinely powerful: wire a gate's output back into its own input, and the circuit's behavior starts depending on its own history — which is exactly what memory is.

The SR Latch: Two Gates, Wired to Remember

The simplest memory element is two NOR gates, cross-coupled — each gate's output feeds into the other gate's input. It has two inputs, S (set) and R (reset), and two outputs, Q and its complement Q'.

The feedback equations

Q = NOR(R, Q'), Q' = NOR(S, Q) — each output depends on the other gate's own current output, not just on S and R directly.

Verified directly — real memory, across a real time sequence

Starting at Q=0: S=1,R=0 (SET) → Q=1. Then S=0,R=0 (HOLD) → Q stays 1. Another S=0,R=0 → still 1. Then S=0,R=1 (RESET) → Q=0. Then two more S=0,R=0 steps → Q stays 0 both times. The exact same inputs (S=0,R=0) produced different Q values depending on what happened earlier — precisely the history-dependence that disqualifies this circuit from being combinational, now demonstrated with a real simulated gate network rather than asserted.

The Forbidden State

A real, verified limitation — not a simplification

S=1, R=1 simultaneously drives both Q and Q' toward 0 — verified directly: both outputs land on 0, breaking the invariant that Q and Q' must always be complements of each other. Real SR latches genuinely forbid this input combination; it's not a corner case this chapter is glossing over, it's a real constraint every actual circuit using an SR latch has to respect.

The D Latch: A Structural Fix

A D latch adds a data input D and an enable line, deriving S and R automatically: S = D · enable, R = D' · enable.

Verified directly — the forbidden state becomes structurally impossible

Checked for all 4 combinations of D and enable: S and R are never both 1 at the same time — because D and D' can never both be 1, whatever gets AND-ed with enable inherits that same guarantee. The forbidden state isn't avoided by careful usage; it's ruled out by the wiring itself.

Level-Triggered vs. Edge-Triggered: Why Flip-Flops Exist

A D latch is level-triggered — while enable stays high, Q tracks D continuously, which can cause real problems when latches are chained (a change can "race" through several stages within a single enable pulse). A D flip-flop is edge-triggered — it only updates at the exact instant a clock signal transitions (e.g. low-to-high), holding steady the rest of the time. This is the real building block used in registers, counters, and pipeline stages, specifically because it makes multi-stage timing predictable.

Real Relevance: This Is What a Variable Actually Is

A CPU register, one bit of RAM, or the value behind an ordinary variable in running code — all the way down at the hardware level — genuinely is one of these feedback circuits. There's no separate "memory technology" beyond this trick, repeated billions of times: writing a variable sets a flip-flop; reading it later returns whatever that flip-flop has been holding since.

Sequential Logic in Code

def NOR(a, b): return 1 - (a | b)

def sr_latch_step(S, R, Q, Qn):
    # iterate the feedback loop until it settles
    for _ in range(10):
        new_Q  = NOR(R, Qn)
        new_Qn = NOR(S, Q)
        if new_Q == Q and new_Qn == Qn:
            break
        Q, Qn = new_Q, new_Qn
    return Q, Qn

Q, Qn = 0, 1
for S, R in [(1,0), (0,0), (0,0), (0,1), (0,0)]:
    Q, Qn = sr_latch_step(S, R, Q, Qn)
    print(f"S={S},R={R}: Q={Q}")   # Q holds its value through every (0,0) step

Hands-On Exercises

Exercise 1

Starting from Q=1, Q'=0, trace this chapter's own SR latch through the sequence (S=0,R=1), (S=0,R=0), (S=0,R=0), (S=1,R=0), showing Q after each step, and confirm Q genuinely holds its value during both (0,0) steps.

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Exercise 2

Using this chapter's own D latch equations (S=D·enable, R=D'·enable), compute S and R for D=1, enable=0, and explain what this means for Q — does the latch update, or hold its previous value? Connect your answer to what "enable" is actually doing.

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Exercise 3

A colleague argues "a D latch can never reach the SR latch's forbidden state, so it must be strictly better and the plain SR latch is obsolete." Using this chapter's own material, explain what's wrong with dismissing the SR latch entirely — specifically, is the SR latch's own S/R behavior ever still useful on its own terms, separate from the forbidden-state issue?

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Chapter 8 Quick Reference

Feedback (a gate's output wired back into its own input) is the mechanism that breaks Chapter 6's own combinational definition and creates memory
SR latch: cross-coupled NOR gates — verified directly to genuinely hold its value across identical S=0,R=0 inputs, depending on prior history
Forbidden state: S=1,R=1 breaks the Q/Q' complement invariant — verified directly, a real constraint
D latch: derives S/R from D and enable so the forbidden state becomes structurally impossible — verified across all 4 combinations
D flip-flop: edge-triggered, not level-triggered — the real building block for registers and multi-stage timing
A variable's stored value, all the way down, genuinely is one of these feedback circuits
Next chapter: Binary, hexadecimal, and number representation