The Sheer Scale of the Instruction Set

Step back from individual instructions for a moment. cpu8bit1-11 formalized RISC vs. CISC using a 56-instruction chip and a ~158-instruction chip as its two data points. This chapter adds the third, modern one — and finds the clean binary that comparison suggested is, at this scale, more complicated than it first looked.

Counting the Instructions — A Genuinely Hard Question

assembly1-5's LC-3 had a small, exact, countable opcode set. cpu8bit1-2 counted 56 6502 mnemonics; cpu8bit1-5 counted roughly 158 for the Z80. x86-64 doesn't have an equally clean number to cite. Base integer instructions alone already number in the hundreds; once every SIMD/vector extension family (assembly2-9's own preview) is counted as its own set of distinct mnemonic-and-operand-form combinations, the real total runs into the thousands. This chapter deliberately doesn't cite one precise figure — pinning down an exact count depends entirely on what's being counted, and a false-precision number would be less honest than admitting the real answer is "a lot, by any reasonable measure, and the exact figure depends on your counting method."

Why So Many — Extending cpu8bit1-5's Own Trick

cpu8bit1-5 explained the Z80's CB/DD/ED/FD prefix bytes as a way to unlock additional opcode spaces beyond a single byte's own 256-value ceiling. x86-64 uses exactly the same underlying idea, stacked several layers deeper: a 0x0F escape byte (in use since the 80386 era) unlocks an entire second opcode table; the REX prefix (already named in assembly2-2 as the mechanism behind SIL/DIL/BPL/SPL and R8–R15 access) unlocks 64-bit operand sizes and the extended register set; and further escape sequences layer entire SIMD instruction families (assembly2-9) on top of all of that. It's the identical mechanism the Z80 pioneered at a small, four-prefix scale — just applied many more times over.

A Brief, Honest Tour of Instruction Categories

Cataloging the full instruction set is explicitly out of scope for this course — instead, a categorized overview:

• Data movement — MOV and its relatives, including MOVZX/MOVSX (zero-extend / sign-extend a smaller value into a larger register), directly relevant to assembly2-2's own sub-register material.
• Arithmetic and logic — ADD/SUB/MUL/DIV/AND/OR/XOR/NOT/NEG, plus specialized variants.
• Control flow — covered in full in assembly2-6.
• String/memory-block instructions — MOVS/CMPS/SCAS/STOS, combined with a REP prefix to repeat an operation across an entire block of memory as one conceptual instruction. A genuinely distinctive x86 family with no real equivalent in LC-3 or the 8-bit chips this arc covered.
• Bit manipulation — instructions like BT/BTS/BTR and POPCNT for testing, setting, and counting individual bits directly.
• System/privileged instructions — previewed fully in assembly2-8.
• SIMD/vector instructions — previewed fully in assembly2-9.

RISC vs. CISC, Confirmed — and Complicated — at Modern Scale

By raw instruction count, x86-64 is exactly what cpu8bit1-11 predicted the Z80 previewed: the CISC trajectory, taken to modern scale.

But the real, honest ending to this comparison is more nuanced than "x86-64 proves CISC won." Modern x86-64 CPUs internally translate their own complex, CISC-style instructions into simpler internal micro-ops, executed on hardware that itself behaves in a genuinely RISC-like way — uniform, pipeline-friendly operations under the hood. The instruction set a programmer writes is CISC; the microarchitecture actually running it, underneath, borrows heavily from RISC's own design lessons. cpu8bit1-11's own clean binary — a chip is either RISC or CISC — was accurate for two 1970s designs studied at the instruction-set level. At this modern scale, the two philosophies don't compete anymore; they coexist inside the same chip, at different layers.

Hands-On Exercises