Exercise 1: What "Packed" Means, and Why ADDPS Replaces Four ADDs — Possible Solution ==================================================================== WHAT "PACKED" MEANS ------------------------------ Per this chapter's own explanation, "packed" describes a single wide register holding MULTIPLE separate data values laid out side by side, rather than one register holding one single value. In the chapter's own example, XMM0 and XMM1 are each 128 bits wide, and each one holds FOUR separate single-precision (32-bit) floating-point values packed together into that one 128-bit register (4 x 32 bits = 128 bits). "Packed" is the term for this multiple-values-in-one-register layout, as opposed to a "scalar" register holding just one value. WHY ONE ADDPS REPLACES FOUR SCALAR ADDS ------------------------------ Per this chapter's own definition, ADDPS performs an ADD operation on ALL FOUR pairs of packed values simultaneously, as a single instruction — the first float in XMM0 is added to the first float in XMM1, the second to the second, and so on, all within the same instruction's own execution. An ordinary scalar ADD instruction can only ever operate on one pair of values at a time, so accomplishing the same four additions without ADDPS would require four SEPARATE ADD (or ADDSS) instructions, each handling exactly one of the four pairs individually, fetched and executed one after another. THE CONCRETE SAVINGS ------------------------------ Where the scalar approach needs 4 separate instructions (plus, typically, separate loads for each individual value), the chapter's own SIMD example needs only 4 instructions TOTAL for the entire operation — two loads (MOVUPS), the actual add (ADDPS), and one store — with the add step itself doing the work of four scalar adds inside a single instruction, rather than needing four of its own. WHY THIS WORKS AS AN ANSWER ------------------------------ It defines "packed" specifically in terms of multiple values sharing one wide register (using the chapter's own 4x32-bit-in-128-bit example), and explains precisely why ADDPS's own simultaneous, all- pairs-at-once behavior is what eliminates the need for four separate scalar ADD instructions, rather than just asserting that SIMD is "faster."