Exercise 3: Why LOOP Is Avoided Despite Resembling DJNZ — Possible Solution
====================================================================

WHY LOOP IS OFTEN AVOIDED IN PRACTICE
------------------------------
Per this chapter's own explanation, LOOP is functionally identical in
spirit to cpu8bit1-8's own Z80 DJNZ — decrement a counter and jump if
it's nonzero, all in one instruction. But on modern x86-64
microarchitectures, an explicit two-instruction sequence (DEC RCX
followed by JNZ) is typically EXECUTED FASTER than the single LOOP
instruction doing the same logical job. This is specifically because
modern CPUs' internal pipelining and instruction-decoding hardware
have been heavily optimized for the ordinary, extremely common
DEC/JNZ pattern, while LOOP itself — a comparatively rare,
specialized instruction in modern code — doesn't benefit from those
same optimizations to nearly the same degree.

WHY THIS IS A FURTHER INSTANCE OF THE SITE'S "RICHNESS ≠ FASTER" THEME
------------------------------
cpu8bit1-7's own cycle-cost table already showed that a more flexible,
capability-richer Z80 addressing mode (IX+d) could cost meaningfully
more in cycles than the 6502's own simpler equivalent. cpu8bit1-8's
own clock-speed caveat showed that raw cycle counts alone, without
real clock-speed context, can give a misleading picture of which chip
is actually faster in practice. LOOP fits the exact same pattern one
level further: it's a genuinely elegant, compact, DJNZ-like
instruction that LOOKS like it should be the efficient choice — yet
in real, modern hardware, the "boring," more explicit two-instruction
alternative wins on actual performance. Across all three cases, the
site's own recurring lesson holds: whether an instruction or mode is
more capable, more compact, or more "advanced-looking" tells you
nothing reliable on its own about whether it's actually faster on
real hardware — that has to be measured, not assumed.

WHY THIS WORKS AS AN ANSWER
------------------------------
It explains the specific, real reason LOOP underperforms on modern
hardware (pipelining optimized for the ordinary DEC/JNZ pattern, not
for LOOP itself), and explicitly connects that finding back to two
earlier, named instances of the exact same "richness/elegance doesn't
guarantee speed" pattern from cpu8bit1-7 and cpu8bit1-8.