Exercise 3: Correcting "The CPU Knows When It's Done" — Possible Solution ==================================================================== THE CORRECTION ------------------------------ The CPU does not "know" a program is done in any meaningful sense. Per the chapter's own tip-box, a CPU has no built-in concept of "finished" or "waiting" at all -- at every single cycle it simply runs the same fetch-decode-execute loop again: fetch whatever instruction the PC currently points at, decode it, execute it, and (unless that instruction changed the PC itself) move on to the next address. This never stops on its own. WHAT ACTUALLY HAPPENS AT EVERY CYCLE ------------------------------ Fetch -> Decode -> (Evaluate Address / Fetch Operands, if needed) -> Execute -> Store Result, then straight back to Fetch again, using whatever the PC now points to. The CPU treats the very last useful instruction of a program exactly the same way it treats the first -- there's no special "end of program" signal built into the hardware itself. HOW A PROGRAM ACTUALLY STOPS ------------------------------ A program stops because it deliberately contains an instruction that tells the CPU to halt -- LC-3's own HALT instruction, previewed in assembly1-1's pipeline example and covered fully in assembly1-8. HALT is fetched, decoded, and executed exactly like any other instruction; the difference is simply that what it DOES is stop the fetch cycle from continuing, rather than adding two numbers or loading a value. If a program never contains a HALT (or some other instruction that stops it), the CPU will just keep fetching and executing whatever bits happen to sit in memory next -- garbage instructions included -- because "the program is logically finished" isn't something the CPU can perceive on its own. WHY THIS WORKS AS AN ANSWER ------------------------------ It directly corrects the false claim using the chapter's own tip-box, restates what happens every cycle in the CPU's own terms (not "it stops," but "it keeps fetching"), and names the specific mechanism -- an explicit HALT instruction -- that actually produces the appearance of a program "finishing."