Exercise 2: Adding +6 and -6 With the Full-Adder Chain — Possible Solution
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STEP 1: ENCODE +6 AND -6 IN 4-BIT TWO'S COMPLEMENT
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+6 = 0110

For -6: invert 0110 -> 1001, then add 1 -> 1010

-6 = 1010

STEP 2: ADD THE TWO PATTERNS THROUGH THE FULL-ADDER CHAIN
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Bits, from least significant (rightmost) to most significant:
+6 = 0 1 1 0
-6 = 1 0 1 0

Stage 0 (bit 0, cin=0): full_adder(0, 0, 0) -> SUM=0, COUT=0
Stage 1 (bit 1, cin=0): full_adder(1, 1, 0) -> SUM=0, COUT=1
Stage 2 (bit 2, cin=1): full_adder(1, 0, 1) -> SUM=0, COUT=1
Stage 3 (bit 3, cin=1): full_adder(0, 1, 1) -> SUM=0, COUT=1

STEP 3: ASSEMBLE THE RESULT
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Result bits (stage 3 down to stage 0): 0 0 0 0
Final carry-out (from stage 3): 1 (discarded)

RESULT
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0000, with the carry-out of 1 correctly discarded (only the 4
result bits are kept in a 4-bit system) - decimal 0, exactly the
correct result of +6 + (-6).

WHY THIS WORKS AS AN ANSWER
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Every stage of the actual full-adder chain from Chapter 7 is
computed explicitly, in the correct bit order (least significant
first, with each stage's carry feeding the next), demonstrating
directly - not just asserting - that unmodified addition hardware
correctly computes a negative-plus-positive result to zero.